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2129b?hirel?12/04 features powerpc ? single issue integer core precise exception model extensive system development support ? on-chip watchpoints and breakpoints ? program flow tracking ? on-chip emulation (once) development interface high performance (dhrystone 2.1: 52 mips at 50 mhz, 3.3v, 1.3 watts total power) low power (< 241 mw at 25 mhz, 2.4v in ternal, 3.3v i/o-core, caches, mmus, i/o) mpc8xx powerpc system interface, includ ing a periodic inte rrupt timer, a bus monitor, and real-time clocks single issue, 32-bit version of the embedded powerpc core (fully compatible with book 1 of the powerpc architecture definition) with 32 32-bit fixed point registers ? embedded powerpc performs branch folding, branch prediction with conditional prefetch, without conditional execution ? 4-kbyte data cache and 4-kbyte instruction cache, each with an mmu ? instruction and data caches are two-way, set associative, physical address, 4 word line burst, least recently used (lru) replacement, lockable on-line granularity ? mmus with 32 entry tlb, fully associative instruction and data tlbs ? mmus support multiple page sizes of 4 kb, 16 kb, 256 kb, 512 kb and 8 mb; 16 virtual address spaces and 8 protection groups ? advanced on-chip emulation debug mode up to 32-bit data bus (dynamic bus sizing for 8- and 16-bit) 32 address lines fully static design v cc = +3.3v 5% f max = 66 mhz military temperature range: -55 c < t c < +125 c p d = 0.75 w typical at 66 mhz description the TSPC860 powerpc quad integrated communication controller (power quicc ? ) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. it particularly excels in communications and networking systems. the power quicc (pronounced ?quick?) can be described as a powerpc-based derivative of the ts68en360 (quicc ? ). the cpu on the TSPC860 is a 32-bit powerpc implementation that incorporates memory management units (mmus) and instruction and data caches. the communi- cations processor module (cpm) of the ts68en360 quicc has been enhanced with the addition of a two-wire interface (twi) compatible with protocols such as i 2 c. mod- erate to high digital signal processing (dsp ) functionality has been added to the cpm. the memory controller has been enhanced, enabling the TSPC860 to support any type of memory, including high performance memories and newer dynamic random access memories (drams). overall system functionality is completed with the addi- tion of a pcmcia socket controller supporting up to two sockets and a real-time clock. pbga 357 zq suffix integrated communication processor TSPC860 preliminary specification -site rev. 2129b?hirel?12/04
2 TSPC860 [preliminary] 2129b?hirel?12/04 screening/quality this product will be manufact ured in full compliance with: according to atmel standards general description the TSPC860 is functionally composed of three major blocks: a 32-bit powerpc core with mmus and caches a system interface unit a communications processor module figure 1. block diagram view of the TSPC860 embedded powerpc core instruction bus 4 or 16 kb i-cache i-mmu scc1 scc2 scc3 scc4 smc1 smc2 spi twi time slot assigner serial interface parallel i/o 16 serial dma and virtual idma memory controller bus interface unit system functions real time clock pcmcia interface baud rate generators parallel interface port timer 32-bit risc controller and program rom mac 4 timers interrupt controller dual-port ram 4 or 8 kb d-cache d-mmu load/store bus unified bus system interface unit
3 TSPC860 [preliminary] 2129b?hirel?12/04 main features the following is a list of the TSPC860?s important features: fully static design four major power saving modes 357-pin ball grid array packaging (plastic) 32-bit address and data busses flexible memory management 4-kbyte physical address, two- way, set-associative data cache 4-kbyte physical address, two-way, set-associative instruction cache eight-bank memory controller ? glueless interface to sram, dram, eprom, flash and other peripherals ? byte write enables and selectable parity generation ? 32-bit address decodes with bit masks system integration unit ? clock synthesizer ? power management ? reset controller ? powerpc decremen ter and time base ? real-time clock register ? periodic interrupt timer ? hardware bus monitor and software watchdog timer ? ieee 1149.1 jtag test access port communications processor module ? embedded 32-bit risc controller architecture for flexible i/o ? interfaces to powerpc core through on-chip dual-port ram and virtual dma channel controller ? continuous mode transmission and reception on all serial channels ? serial dma channels for reception and transmission on all serial channels ? i/o registers with open-drain capability ? memory-memory and memory-i/o transfers with virtual dma functionality
4 TSPC860 [preliminary] 2129b?hirel?12/04 four serial communications controllers ? protocols supported by rom or downloadable microcode and include, but limited to, the digital portion of: - ethernet/ieee 802.3 cs/cdma - hdlc/sdlc and hdlc bus - apple talk - signaling system #7 (ram microcode only) - universal asynchronous re ceiver transmitter (uart) - synchronous uart - binary synchronous (bisync) communications - totally transparent - totally transparent with crc - profibus (ram microcode option) - asynchronous hdlc - ddcmp - v.14 (ram microcode option) - x.21 (ram microcode option) - v.32bis datapump filters - irda serial infrared - basis rate isdn (bri) in conjunction with smc channels - primary rate isdn (mh version only) ? four hardware serial communications controller channels supporting the protocols ? two hardware serial management channels - management for bri devices as general circuit interface controller multiplexed channels - low-speed uart operation ? hardware serial peripheral interfaces ? two-wire interface (twi) ? time-slot assigner ? port supports centronics interfaces and chip-to-chip ? four independent baud rate generators and four input clock pins for supplying clocks to smc and scc serial channels ? four independent 16-bit timers which can be interconnected as two 32-bit timers
5 TSPC860 [preliminary] 2129b?hirel?12/04 pin assignment plastic ball grid array figure 2. pin assignment: top view pd3 irq7 d0 d4 d1 d2 d3 d5 vddl d6 d7 d29 clkout ipa3 dp2 a2 a7 a14 a27 a29 a30 a28 a31 vddl bsa2 we1 we3 ce2a cs1 cs4 a5 a11 18 16 14 13 12 11 10 9 8 7 6 5 3 2 4 17 15 1 19 a1 a6 a13 a17 a21 a23 a22 tsiz0 bsa3 m_crs we2 gpla2 ce1a wr cs5 a4 a10 gplb4 a0 pa15 a3 a12 a16 a20 a24 a26 tsiz1 bsa1 we0 gpla1 gpla3 cs0 ta cs7 pb31 a9 gpla4 pb30 pc14 pc15 n/c n/c a15 a19 a25 a18 bsa0 gpla0 n/c cs6 gpla5 bdip cs2 pa14 a8 tea pb28 pc13 pb29 vddh vddh bi bg cs3 pa13 bb pb27 pc12 vddl gnd gnd ts irq3 vddl pa12 burst pb26 tms pa11 irq6 ipb4 br tdo ipb3 trst m_mdio tck irq2 ipb0 m_col tdi ipb7 vddl pb24 pb25 ipb1 ipb2 ipb5 pa10 aleb pc11 pa9 pb21 gnd ipb6 alea baddr30 pb23 irq4 pc10 pc9 pb20 as op1 op0 pa8 modck1 pb22 pc8 pc7 baddr28 baddr29 modck2 pa6 vddl pa7 pa5 pb16 texp extclk hreset pb18 extal pb19 pb17 vddl gnd rstconf sreset vddl pa3 gnd xtal pa4 pa2 pd12 vddh wait _a poreset wait _b pb15 vddh kapwr pc6 pc5 pd11 vddh d12 d17 d9 d15 d22 d25 d31 ipa6 ipa0 ipa7 xfc ipa1 pc4 pd7 vddsyn pa1 pb14 pd4 irq1 d8 d23 d11 d16 d19 d21 d26 d30 ipa5 ipa2 n/c ipa4 pd15 pd5 vsssyn pa0 pd13 pd6 irq0 d13 d27 d10 d14 d18 d20 d24 d28 dp1 dp0 n/c dp3 pd9 m_tx_en vsssyn1 pd14 b a c d e f g h j k l m n p r t u v w pd10 pd8
6 TSPC860 [preliminary] 2129b?hirel?12/04 signal description this section describes the signals on the TSPC860. figure 3. TSPC860 external signals 129 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32 1 1 1 1 1 1 1 1 1 1 1 1 32 4 1 1 1 1 2 1 6 1 1 1 1 1 1 4 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 5 1 1 2 1 1 1 1 1 2 1 1 1 1 1 TSPC860 a(0:31) tsiz0/reg tsiz1 rd/wr burst bdip/gpl_b(5) ts ta tea bi irq2/rsv irq4/kr/retry/spkrout cr/irq3 d(0:31) dp(0:3)/irq(3:6) br bg bb frz/irq6 irq(0:1) irq(7) cs(0:5) cs(6)/ce(1)_b cs(7)/ce(2)_b we0/bs_b0/iord we1/bs_b1/iowr we2/bs_b2/pcoe we3/bs_b3/pcwe bs_a(0:3) gpl_a0/gpl_b0 oe/gpl_a1/gpl_b1 gpl_a(2:3)/gpl_b(2:3)/cs(2:3) upwaita/gpl_a4 upwaitb/gpl_b4 gpl_a5 poreset rstconf hreset sreset xtal extal xfc clkout extclk texp ale_a ce1_a ce2_a wait_a ip_a(0:1) ip_a2/iois16_a ip_a(3:7) ale_b/dsck/at1 wait_b ip_b(0:1)/iwp(0:1)/vfls(0:1) ip_b2/iois16_b/at2 ip_b3/iwp2/vf2 ip_b4/lwp0/vf0 ip_b5/lwp1/vf1 ip_b6/dsdi/at0 ip_b7/ptr/vat3 op(0:1) op2/modck1/sts op3/modck2/dsdo baddr30/reg baddr(28:29) vddsyn/vsssyn/vsssyn1/vddh/vddl/vss/kapwr rxd1/pa[15] txd1/pa[14] rxd2/pa[13] txd2/pa[12] l1txdb/pa[11] l1rxdb/pa[10] l1txda/pa[9] l1rxda/pa[8] tin1/l1rclka/brgo1/clk1/pa[7] brgclk1/tout1/clk2/pa[6] tin2/l1tclka/brgo2/clk3/pa[5] tout2/clk4/pa[4] tin3/brgo3/clk5/pa[3] brgclk2/l1rclkb/tout3/clk6/pa[2] tin4/brgo4/clk7/pa[1] l1tclkb/tout4/clk8/pa[0] reject1/spisel/pb[31] spiclk/pb[30] spimosi/pb[29] brgo4/spimiso/pb[28] brgo1/i2csda/pb[27] brgo2/i2cscl/pb[26] smtxd1/pb[25] smrxd1/pb[24] smsyn1/sdack1/pb[23] smsyn2/sdack2/pb[22] smtxd2/l1clkob/pb[21] smrxd2/l1clkoa/pb[20] l1st1/rts1/pb[19] l1st2/rts2/pb[18] l1st3/l1rqb/pb[17] l1st4/l1rqa/pb[16] brgo3/pb[15] rstrt1/pb[14] l1st1/rts1/dreq0/pc[15] l1st2v/rts2/dreq1/pc[14] l1st3/l1rqb/pc[13] l1st4/l1rqa/pc[12] cts1/pc[11] tgate1/cd1/pc[10] cts2/pc[9] tgate2/cd2/pc[8] cts3/sdack2/l1tsyncb/pc[7] cd3/l1rsyncb/pc[6] cts4/sdack1/l1tsynca/pc[5] cd4/l1rsynca/pc[4] l1tsynca/pd[15] l1rsynca/pd[14] l1tsyncb/pd[13] l1rsyncb/pd[12] rxd3/pd[11] txd3/pd[10] rxd4/pd[9] txd4/pd[8] rts3/pd[7] rts4/pd[6] reject2/pd[5] reject3/pd[4] reject4/pd[3] tms dsdi/tdi dsck/tck trst dsdo/tdo as
7 TSPC860 [preliminary] 2129b?hirel?12/04 figure 4. TSPC860 signals and pin numbers (part 1)
8 TSPC860 [preliminary] 2129b?hirel?12/04 figure 5. TSPC860 signals and pin numbers (part 2)
9 TSPC860 [preliminary] 2129b?hirel?12/04 system bus signals the TSPC860 system bus consists of all si gnals that interface with the external bus. many of these signals perform different fu nctions, depending on how the user assigns them. the following input and output signals are identified by their abbreviation. each signal?s pin number can be found in figure 4 and figure 5. table 1. signal descriptions name reset number type description a(0-31) hi-z see figure 2 bidirectional three-state address bus?provides the address fo r the current bus cycle. a0 is the most-significant signal. the bus is output when an internal master starts a transaction on the external bus. the bus is input when an external master starts a transaction on the bus. tsiz0 reg hi-z b9 bidirectional three-state transfer size 0?when accessing a slave in the external bus, used (together with tsiz1) by the bus master to indicate the number of operand bytes waiting to be tran sferred in the current bus cycle. tsiz0 is an input when an external master starts a bus transaction. register?when an internal master initiates an access to a slave controlled by the pcmcia interface, reg is output to indicate which space in the pcmcia card is accessed. tsiz1 hi-z c9 bidirectional three-state transfer size 1?used (with tsiz0) by the bus master to indicate the number of operand bytes waiting to be transferred in the current bus cycle. the TSPC860 drives tsiz1 w hen it is bus master. tsiz1 is input when an external master starts a bus transaction. rd/wr hi-z b2 bidirectional three-state read/write?driven by the bus master to indicate the direction of the bus?s data transfer. a logic one indi cates a read from a slave device and a logic zero indicates a write to a slave device. the TSPC860 drives this signal when it is bus master. input when an external master initiates a transaction on the bus. burst hi-z f1 bidirectional three-state burst transaction?driven by the bus master to indicate that the current initiated transfer is a burst. the TSPC860 drives this signal when it is bus master. this signal is input when an external master initiates a transaction on the bus. bdip gpl_b 5 see section ?signal states during hardware reset? on page 27 d2 bidirectional three-state burst data in progress?when a ccessing a slave device in the external bus, the master on the bus asserts this signal to indicate that the data beat in front of the current one is the one requested by the master. bdip is negated before the expected last data beat of the burst transfer. general-purpose line b5-used by the memory controller when upmb takes control of the slave access. ts hi-z f3 bidirectional active pull-up transfer start?asserted by the bus master to indicate the start of a bus cycle that transfers data to or from a slave device. driven by the master only when it has gained the ownership of the bus. every master should negate this signal before the bus relinquish. ts requires the use of an external pull-up resistor. the TSPC860 samples ts when it is not the external bus master to allow the memory controller/pcmcia interface to control the accessed slave device. it indicate s that an external synchronous master initiated a transaction.
10 TSPC860 [preliminary] 2129b?hirel?12/04 ta hi-z c2 bidirectional active pull-up transfer acknowledge?indicates that the slave device addressed in the current transaction accepted data sent by the master (write) or has driven the data bus with valid data (read). this is an output when the pcmcia interface or memory co ntroller controls the transaction. the only exception occurs when the memory controller controls the slave access by means of the gpcm and the corresponding option register is instructed to wait for an external assertion of ta . every slave device should negate ta after a transaction ends and immediately three-state it to avoid bus contention if a new transfer is initiated addressing other slave devices. ta requires the use of an external pull-up resistor. tea hi-z d1 open-drain transfer error acknowledge?indicates that a bus error occurred in the current transaction. the TSPC860 asserts tea when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. asserting tea terminates the bus cycle, thus ignoring the state of ta . tea requires the use of an external pull-up resistor. bi hi-z e3 bidirectional active pull-up burst inhibit?indicates that the slave device addressed in the current burst transaction cannot support burst transfers. it acts as an output when the pcmcia interfac e or the memory controller takes control of the transaction. bi requires the use of an external pull-up resistor. rsv irq2 see section ?signal states during hardware reset? on page 27 h3 bidirectional three-state reservation?the TSPC860 outputs this three-state signal in conjunction with the address bus to indicate that the core initiated a transfer as a result of a stwcx. or lwarx. interrupt request 2?one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. kr /retry irq4 spkrout see section ?signal states during hardware reset? on page 27 k1 bidirectional three-state kill reservation?this input is used as a part of the memory reservation protocol, when the TSPC860 initiated a transaction as the result of a stwcx. instruction. retry?this input is used by a slave device to indicate it cannot accept the transaction. the tspc 860 must relinquish mastership and reinitiate the transaction after winning in the bus arbitration. interrupt request 4 ? one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal that is sent to the interrupt controller is the logical and of this line (if defined as irq4 ) and dp1/irq4 (if defined as irq4 ). spkrout?digital audio wave form output to be driven to the system speaker. cr irq3 hi-z f2 input cancel reservation?this inpu t is used as a part of the storage reservation protocol. interrupt request 3?one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal sent to the interrupt controller is the logical and of cr /irq3 (if defined as irq3 ) and dp0/irq3 if defined as irq3 . table 1. signal descriptions (continued) name reset number type description
11 TSPC860 [preliminary] 2129b?hirel?12/04 d(0-31) hi-z (pulled low if rstconf pulled down) see figure 2 bidirectional three-state data bus?this bidirectional three-state bus provides the general- purpose data path between the TSPC860 and all other devices. the 32-bit data path can be dynamically sized to support 8-, 16-, or 32-bit transfers. d0 is the msb of the data bus. dp0 irq3 hi-z v3 bidirectional three-state data parity 0?provides parity generation and checking for d(0-7) for transfers to a slave device initiated by the TSPC860. the parity function can be defined independent ly for each one of the addressed memory banks (if controlled by t he memory controller) and for the rest of the slaves sitting on the external bus. parity generation and checking is not supported for external masters. interrupt request 3?one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal sent to the interrupt controller is the logical and of dp0/irq3 (if defined as irq3 ) and cr /irq3 (if defined as irq3 ). dp1 irq4 hi-z v5 bidirectional three-state data parity 1?provides parity generation and checking for d(8-15) for transfers to a slave device initiated by the TSPC860. the parity function can be defined independent ly for each one of the addressed memory banks (if controlled by t he memory controller) and for the rest of the slaves on the external bus. parity generation and checking is not supported for external masters. interrupt request 4?one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal sent to the interrupt controller is the logical and of this line (if defined as irq4 ) and kr /irq4 /spkrout (if defined as irq4 ). dp2 irq5 hi-z w4 bidirectional three-state data parity 2?provides parity generation and checking for d(16-23) for transfers to a slave device initiated by the TSPC860. the parity function can be defined independent ly for each one of the addressed memory banks (if controlled by t he memory controller) and for the rest of the slaves on the external bus. parity generation and checking is not supported for external masters. interrupt request 5?one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. dp3 irq6 hi-z v4 bidirectional three-state data parity 3?provides parity generation and checking for d(24-31) for transfers to a slave device initiated by the TSPC860. the parity function can be defined independent ly for each one of the addressed memory banks (if controlled by t he memory controller) and for the rest of the slaves on the external bus. parity generation and checking is not supported for external masters. interrupt request 6?one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal sent to the interrupt controller is the logical and of this line (if defined as irq6 ) and the frz/irq6 (if defined as irq6 ). br hi-z g4 bidirectional bus request?asserted lo w when a possible master is requesting ownership of the bus. when the TSPC860 is configured to work with the internal arbiter, this signal is configured as an input. when the TSPC860 is configured to work with an external arbiter, this signal is configured as an output and asserted every time a new transaction is intended to be initiated (no parking on the bus). table 1. signal descriptions (continued) name reset number type description
12 TSPC860 [preliminary] 2129b?hirel?12/04 bg hi-z e2 bidirectional bus grant?asserted low when the arbiter of the external bus grants the bus to a specific device. when the TSPC860 is configured to work with the internal arbiter, bg is configured as an output and asserted every time the external master asserts br and its priority request is higher than any internal sources requiring a bus transfer. however, when the TSPC860 is configured to work with an external arbiter, bg is an input. bb hi-z e1 bidirectional active pull-up bus busy?asserted low by a master to show that it owns the bus. the TSPC860 asserts bb after the arbiter gr ants it bus ownership and bb is negated. frz irq6 see section ?signal states during hardware reset? on page 27 g3 bidirectional freeze?output asserted to indicate that the core is in debug mode. interrupt request 6?one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal sent to the interrupt controller is the logical and of frz/irq6 (if defined as irq6 ) and dp3/irq6 (if defined as irq6 ). irq0 hi-z v14 input interrupt request 0?one of ei ght external inputs that can request (by means of the internal interrupt controller) a service routine from the core. irq1 hi-z u14 input interrupt request 1?one of ei ght external inputs that can request (by means of the internal interrupt controller) a service routine from the core. irq7 hi-z w15 input interrupt request 7?one of ei ght external inputs that can request (by means of the internal interrupt controller) a service routine from the core. cs (0-5) high c3, a2, d4, e4, a4, b4 output chip select?these outputs enable peripheral or memory devices at programmed addresses if they are appropriately defined. cs0 can be configured to be the global chip-select for the boot device. cs6 ce1_b high d5 output chip select 6?this output enables a peripheral or memory device at a programmed address if defined appropriately in the br6 and or6 in the memory controller. card enable 1 slot b?this output enables even byte transfers when accesses to the pcmcia slot b ar e handled under the control of the pcmcia interface. cs7 ce2_b high c4 output chip select 7?this output enables a peripheral or memory device at a programmed address if defined appropriately in the br7 and or7 in the memory controller. card enable 2 slot b?this output enables odd byte transfers when accesses to the pcmcia slot b ar e handled under the control of the pcmcia interface. table 1. signal descriptions (continued) name reset number type description
13 TSPC860 [preliminary] 2129b?hirel?12/04 we0 bs_b0 iord high c7 output write enable 0?output asserted when a write access to an external slave controlled by the gpcm is initiated by the TSPC860 . we0 is asserted if d(0-7) contains valid data to be stored by the slave device. byte select 0 on upmb?output asserted under control of the upmb, as programmed by the user. in a read or write transfer, the line is only asserted if d(0-7) contains valid data. io device read?output asserted when the TSPC860 starts a read access to a region controlled by the pcmcia interface. asserted only for accesses to a pc card i/o space. we1 bs_b1 iowr high a6 output write enable 1?output a sserted when the TSPC860 initiates a write access to an external slave controlled by the gpcm. we1 is asserted if d(8-15) contains valid data to be stored by the slave device. byte select 1 on upmb?output asserted under control of the upmb, as programmed by the user. in a read or write transfer, the line is only asserted if d(8-15) contains valid data. i/o device write?this output is asserted when the TSPC860 initiates a write access to a region controlled by the pcmcia interface. iowr is asserted only if the access is to a pc card i/o space. we2 bs_b2 pcoe high b6 output write enable 2?output asse rted when the TSPC860 starts a write access to an external slave controlled by the gpcm. we2 is asserted if d(16-23) contains valid data to be stored by the slave device. byte select 2 on upmb?output asserted under control of the upmb, as programmed by the user. in a read or write transfer, bs_b2 is asserted only d(16-23) contains valid data. pcmcia output enable?output asserted when the TSPC860 initiates a read access to a memory region under the control of the pcmcia interface. we3 bs_b3 pcwe high a5 output write enable 3?output a sserted when the TSPC860 initiates a write access to an external slave controlled by the gpcm. we3 is asserted if d(24-31) contains valid data to be stored by the slave device. byte select 3 on upmb?output asserted under control of the upmb, as programmed by the user. in a read or write transfer, bs_b3 is asserted only if d(24-31) contains valid data. pcmcia write enable?output asserted when the TSPC860 initiates a write access to a memory region under control of the pcmcia interface. bs_a (0-3) high d8, c8, a7, b8 output byte select 0 to 3 on upma?o utputs asserted under requirement of the upmb, as programmed by the user. for read or writes, asserted only if their corresponding data lanes contain valid data: bs_a0 for d(0-7), bs_a1 for d(8-15), bs_a2 for d(16-23), bs_a3 for d(24-31) table 1. signal descriptions (continued) name reset number type description
14 TSPC860 [preliminary] 2129b?hirel?12/04 gpl_a0 gpl_b0 high d7 output general-purpose line 0 on upma?this output reflects the value specified in the upma when an external transfer to a slave is controlled by the upma. general-purpose line 0 on upmb?this output reflects the value specified in the upmb when an external transfer to a slave is controlled by the upmb. oe gpl_a1 gpl_b1 high c6 output output enable?o utput asserted when the TSPC860 initiates a read access to an external slav e controlled by the gpcm. general-purpose line 1 on upma?this output reflects the value specified in the upma when an external transfer to a slave is controlled by upma. general-purpose line 1 on upmb?this output reflects the value specified in the upmb when an external transfer to a slave is controlled by upmb. gpl_a (2-3) gpl_b (2-3) cs (2-3) high b5, c5 output general-purpose line 2 and 3 on upma?these outputs reflect the value specified in the upma when an external transfer to a slave is controlled by upma. general-purpose line 2 and 3 on upmb?these outputs reflect the value specified in the upmb when an external transfer to a slave is controlled by upmb. chip select 2 and 3?these outputs enable peripheral or memory devices at programmed addresses if they are appropriately defined. the double drive capability for cs2 and cs3 is independently defined for each signal in the siumcr. upwaita gpl_a4 hi-z c1 bidirectional user programmable machine wait a?this input is sampled as defined by the user when an access to an external slave is controlled by the upma. general-purpose line 4 on upma?this output reflects the value specified in the upma when an external transfer to a slave is controlled by upma. upwaitb gpl_b4 hi-z b1 bidirectional user programmable machine wait b?this input is sampled as defined by the user when an access to an external slave is controlled by the upmb. general-purpose line 4 on upmb?this output reflects the value specified in the upmb when an external transfer to a slave is controlled by upmb. gpl_a5 high d3 output general-purpose line 5 on upma?this output reflects the value specified in the upma when an external transfer to a slave is controlled by upma. this signal can also be controlled by the upmb. poreset hi-z r2 input power on reset?when asserted, this input causes the TSPC860 to enter the power-on reset state. rstconf hi-z p3 input reset configuration?the TSPC860 samples this input while hreset is asserted. if rstconf is asserted, the configuration mode is sampled in the form of the hard reset configuration word driven on the data bus. when rstconf is negated, the TSPC860 uses the default configuration mode. note that the initial base address of internal registers is determined in this sequence. hreset low n4 open-drain hard reset?asserting this open drain signal puts the TSPC860 in hard reset state. table 1. signal descriptions (continued) name reset number type description
15 TSPC860 [preliminary] 2129b?hirel?12/04 sreset low p2 open-drain soft reset?asserting this open drain line puts the TSPC860 in soft reset state. xtal analog driving p1 analog output this output is one of the connections to an external crystal for the internal oscillator circuitry. extal hi-z n1 analog input (3.3v only) this line is one of the connections to an external crystal for the internal oscillator circuitry. xfc analog driving t2 analog input external filter capacitance? this input is the connection pin for an external capacitor filter for the pll circuitry. clkout high until spll locked, then oscillating w3 output clock out?this output is the clock system frequency. extclk hi-z n2 input (3.3v only) external clock ? this input is the external input clock from an external source. texp high n3 output timer expired?this output reflects the status of plprcr[texps]. ale_a low k2 output address latch enable a? this output is asserted when TSPC860 initiates an access to a region under the control of the pcmcia interface to socket a. ce1_a high b3 output card enable 1 slot a?this output enables even byte transfers when accesses to pcmcia slot a are handled under the control of the pcmcia interface. ce2_a high a3 output card enable 2 slot a?this output enables odd byte transfers when accesses to pcmcia slot a are handled under the control of the pcmcia interface. wait_a hi-z r3 input wait slot a?this input, if asserted low, causes a delay in the completion of a transaction on the pcmcia controlled slot a. wait_b hi-z r4 input wait slot b?this input, if asserted low, causes a delay in the completion of a transaction on the pcmcia controlled slot b. ip_a(0-1) hi-z t5, t4 input input port a 0-1?th e TSPC860 monitors these inputs that are reflected in the pipr and pscr of the pcmcia interface. ip_a2 iois16_a hi-z u3 input input port a 2?the TSPC860 monitors these inputs; its value and changes are reported in the pipr and pscr of the pcmcia interface. i/o device a is 16-bits ports si ze?the TSPC860 monitors this input when a transaction under the control of the pcmcia interface is initiated to an i/o region in socket a of the pcmcia space. ip_a(3-7) hi-z w2, u4, u5, t6, t3 input input port a 3-7?the TSPC860 monitors these inputs; their values and changes are reported in the pipr and pscr of the pcmcia interface. table 1. signal descriptions (continued) name reset number type description
16 TSPC860 [preliminary] 2129b?hirel?12/04 ale_b dsck/at1 see section ?signal states during hardware reset? on page 27 j1 bidirectional three-state address latch enable b?this output is asserted when the TSPC860 initiates an access to a re gion under the control of the pcmcia socket b interface. development serial clock?this input is the clock for the debug port interface. address type 1?the TSPC860 drives this bidirectional three-state line when it initiates a transaction on the external bus. when the transaction is initiated by the core, it indicates if the transfer is for user or supervisor state. this signal is not used for transactions initiated by external masters. ip_b(0-1) iwp(0-1) vfls(0-1) see section ?signal states during hardware reset? on page 27 h2, j3 bidirectional input port b 0-1?the TSPC860 senses these inputs; their values and changes are reported in the pipr and pscr of the pcmcia interface. instruction watchpoint 0-1?these outputs report the detection of an instruction watchpoint in the program flow executed by the core. visible history buffer flushes status?the TSPC860 outputs vfls(0-1) when program instruction flow tracking is required. they report the number of instructions flushed from the history buffer in the core. ip_b2 iois16_b at 2 hi-z j2 bidirectional three-state input port b 2?the TSPC860 senses this input; its value and changes are reported in the pipr and pscr of the pcmcia interface. i/o device b is 16- bits port si ze?the TSPC860 monitors this input when a pcmcia interface transaction is initiated to an i/o region in socket b in the pcmcia space. address type 2?the TSPC860 drives this bidirectional three-state signal when it initiates a transaction on the external bus. if the core initiates the transaction, it indicates if the transfer is instruction or data. this signal is not used for transactions initiated by external masters. ip_b3 iwp2 vf2 see section ?signal states during hardware reset? on page 27 g1 bidirectional input port b 3 ? the TSPC860 monitors this input; its value and changes are reported in the pipr and pscr of the pcmcia interface. instruction watchpoint 2?this outp ut reports the detection of an instruction watchpoint in the program flow executed by the core. visible instruction queue flush status?the TSPC860 outputs vf2 with vf0/vf1 when instruction flow tracking is required. vfn reports the number of instructions flushed from the instruction queue in the core. ip_b4 lwp0 vf0 hi-z g2 bidirectional input port b 4?the TSPC860 monitors this input; its value and changes are reported in the pipr and pscr of the pcmcia interface. load/store watchpoint 0?this ou tput reports the detection of a data watchpoint in the program flow executed by the core. visible instruction queue flus hes status?the TSPC860 outputs vf0 with vf1/vf2 when instruction flow tracking is required. vfn reports the number of instructions flushed from the instruction queue in the core. table 1. signal descriptions (continued) name reset number type description
17 TSPC860 [preliminary] 2129b?hirel?12/04 ip_b5 lwp1 vf1 hi-z j4 bidirectional input port b 5?the TSPC860 monitors this input; its value and changes are reported in the pipr and pscr of the pcmcia interface. load/store watchpoint 1?this ou tput reports the detection of a data watchpoint in the program flow executed by the core. visible instruction queue flus hes status?the TSPC860 outputs vf1 with vf0 and vf2 when instruction flow tracking is required. vfn reports the number of instruct ions flushed from the instruction queue in the core. ip_b6 dsdi at 0 hi-z k3 bidirectional three-state input port b 6?the TSPC860 senses this input and its value and changes are reported in the pipr and pscr of the pcmcia interface. development serial data input? data input for the debug port interface. address type 0?the TSPC860 drives this bidirectional three-state line when it initiates a transaction on the external bus. if high (1), the transaction is the cpm. if low (0), the transaction initiator is the cpu. this signal is not used for transactions initiated by external masters. ip_b7 ptr at 3 hi-z h1 bidirectional three-state input port b 7?the TSPC860 monitors this input; its value and changes are reported in the pipr and pscr of the pcmcia interface. program trace?to allow program flow tracking, the TSPC860 asserts this output to indicate an instruction fetch is taking place. address type 3?the TSPC860 drives the bidirectional three-state signal when it starts a transaction on the external bus. when the core initiates a transfer, at3 indicates whether it is a reservation for a data transfer or a program trace indication for an instruction fetch. this signal is not used for transactions initiated by external masters. op(0-1) low l4, l2 output output port 0-1?the t spc860 generates these outputs as a result of a write to the pgcra regist er in the pcmcia interface. op2 modck1 sts hi-z l1 bidirectional output port 2?this output is generated by the TSPC860 as a result of a write to the pgcrb regist er in the pcmcia interface. mode clock 1?input sampled when poreset is negated to configure pll/clock mode. special transfer start?the TSPC860 drives this output to indicate the start of an external bus transfer or of an internal transaction in show-cycle mode. op3 modck2 dsdo hi-z m4 bidirectional output port 3?this output is generated by the TSPC860 as a result of a write to the pgcrb regist er in the pcmcia interface. mode clock 2?this input is sampled at the poreset negation to configure the pll/clock mode of operation. development serial data output?o utput data from the debug port interface. table 1. signal descriptions (continued) name reset number type description
18 TSPC860 [preliminary] 2129b?hirel?12/04 baddr30 reg hi-z k4 output burst address 30?this output duplicates the value of a30 when the following is true: ? an internal master in the TSPC860 initiates a transaction on the external bus ? an asynchronous external master initiates a transaction ? a synchronous external master initiates a single beat transaction the memory controller uses baddr30 to increment the address lines that connect to memory devices when a synchronous external master or an internal master initiates a burst transfer. register?when an internal master initiates an access to a slave under control of the pcmcia interface, this signal duplicates the value of tsiz0/reg . when an external master initiates an access, reg is output by the pcmcia interface (if it must handle the transfer) to indicate the space in the pcmcia card being accessed. baddr(28- 29) hi-z m3 m2 output burst address?outputs that duplic ate a(28-29) valu es when one of the following occurs: ? an internal master in the TSPC860 initiates a transaction on the external bus ? an asynchronous external master initiates a transaction ? a synchronous external master initiates a single beat transaction the memory controller uses these signals to increment the address lines that connect to memory devices when a synchronous external or internal master starts a burst transfer. as hi-z l3 input address strobe?input driven by an external asynchronous master to indicate a valid address on a(0-31). the TSPC860 memory controller synchronizes as and controls the memory device addressed under its control. pa [ 1 5 ] rxd1 hi-z c18 bidirectional general-purpose i/o port a bit 15?bit 15 of the general-purpose i/o port a. rxd1?receive data input for scc1. pa [ 1 4 ] txd1 d17 bidirectional (optional: open-drain) general-purpose i/o port a bit 14?bit 14 of the general-purpose i/o port a. txd1?transmit data output for scc1. txd1 has an open-drain capability. pa [ 1 3 ] rxd2 e17 bidirectional general-purpose i/o port a bit 13?bit 13 of the general-purpose i/o port a. rxd2?receive data input for scc2. pa [ 1 2 ] txd2 f17 bidirectional (optional: open-drain) general-purpose i/o port a bit 12?bit 12 of the general-purpose i/o port a. txd2?transmit data output for scc2. txd2 has an open-drain capability. pa [ 1 1 ] l1txdb g16 bidirectional (optional: open-drain) general-purpose i/o port a bit 11?bit 11 of the general-purpose i/o port a. l1txdb?transmit data output for the serial interface tdm port b. l1txdb has an open-drain capability. pa [ 1 0 ] l1rxdb j17 bidirectional general-purpose i/o port a bit 10?bit 10 of the general-purpose i/o port a. l1rxdb?receive data input for the serial interface tdm port b. table 1. signal descriptions (continued) name reset number type description
19 TSPC860 [preliminary] 2129b?hirel?12/04 pa [ 9 ] l1txda k18 bidirectional (optional: open-drain) general-purpose i/o port a bit 11?bit 9 of the general-purpose i/o port a. l1txda?transmit data output for the serial interface tdm port a. l1txda has an open-drain capability. pa [ 8 ] l1rxda l17 bidirectional general-purpose i/o port a bit 8?bit 8 of the general-purpose i/o port a. l1rxda?receive data input for the serial interface tdm port a. pa [ 7 ] clk1 tin1 l1rclka brgo1 m19 bidirectional general-purpose i/o port a bit 7?bit 7 of the general-purpose i/o port a. clk1?one of eight clock inputs that can be used to clock sccs and smcs. tin1?timer 1 external clock. l1rclka?receive clock for the serial interface tdm port a. brgo1?output clock of brg1. pa [ 6 ] clk2 tout1 brgclk1 m17 bidirectional general-purpose i/o port a bit 6?bit 6 of the general-purpose i/o port a. clk2?one of eight clock inputs that can be used to clock sccs and smcs. tout1 ?timer 1 output. brgclk1?one of two external clock inputs of the brgs. pa [ 5 ] clk3 tin2 l1tclka brgo2 n18 bidirectional general-purpose i/o port a bit 5?bit 5 of the general-purpose i/o port a. clk3?one of eight clock inputs that can be used to clock sccs and smcs. tin2?timer 2 external clock input. l1tclka?transmit clock for the serial interface tdm port a. brgo2?output clock of brg2. pa [ 4 ] clk4 tout2 hi-z p19 bidirectional general-purpose i/o port a bit 4?bit 4 of the general-purpose i/o port a. clk4?one of eight clock inputs that can be used to clock sccs and smcs. tout2 ?timer 2 output. pa [ 3 ] clk5 tin3 brgo3 p17 bidirectional general-purpose i/o port a bit 3?bit 3 of the general-purpose i/o port a. clk5?one of eight clock inputs that can be used to clock sccs and smcs. tin3?timer 3 external clock input. brgo3?output clock of brg3. pa [ 2 ] clk6 tout3 l1rclkb brgclk2 r18 bidirectional general-purpose i/o port a bit 2?bit 2 of the general-purpose i/o port a. clk6?one of eight clock inputs that can be used to clock the sccs and smcs. tout3 ?timer 3 output. l1rclkb?receive clock for the serial interface tdm port b. brgclk2?one of the two external clock inputs of the brgs. table 1. signal descriptions (continued) name reset number type description
20 TSPC860 [preliminary] 2129b?hirel?12/04 pa [ 1 ] clk7 tin4 brgo4 t19 bidirectional general-purpose i/o port a bit 1?bit 1 of the general-purpose i/o port a. clk7?one of eight clock inputs that can be used to clock sccs and smcs. tin4?timer 4 external clock input. brgo4?brg4 output clock. pa [ 0 ] clk8 tout4 l1tclkb u19 bidirectional general-purpose i/o port a bit 0?bit 0 of the general-purpose i/o port a. clk8?one of eight clock inputs that can be used to clock sccs and smcs. tout4 ?timer 4 output. l1tclkb?transmit clock for the serial interface tdm port b. pb[31] spisel reject1 c17 bidirectional (optional: open-drain) general-purpose i/o port b bit 31?bit 31 of the general-purpose i/o port b. spisel ?spi slave select input. reject1 ?scc1 cam interface reject pin. pb[30] spiclk rstrt2 c19 bidirectional (optional: open-drain) general-purpose i/o port b bit 30?bit 30 of the general-purpose i/o port b. spiclk?spi output clock when it is configured as a master or spi input clock when it is configured as a slave. rstrt2 ?scc2 serial cam interface output signal that marks the start of a frame. pb[29] spimosi e16 bidirectional (optional: open-drain) general-purpose i/o port b bit 29?bit 29 of the general-purpose i/o port b. spimosi?spi output data when it is configur ed as a master or spi input data when it is configured as a slave. pb[28] spimiso brgo4 d19 bidirectional (optional: open-drain) general-purpose i/o port b bit 28?bit 29 of the general-purpose i/o port b. spimiso?spi input da ta when the TSPC860 is a master; spi output data when it is a slave. brgo4?brg4 output clock. pb[27] i2csda brgo1 hi-z e19 bidirectional (optional: open-drain) general-purpose i/o port b bit 27?bit 27 of the general-purpose i/o port b. i2csda? twi serial data pin. bidirectional; should be configured as an open-drain output. brgo1?brg1 output clock. pb[26] i2cscl brgo2 f19 bidirectional (optional: open-drain) general-purpose i/o port b bit 26?bit 26 of the general-purpose i/o port b. i2cscl? twi serial clock pin. bidirectional; should be configured as an open-drain output. brgo2?brg2 output clock. pb[25] smtxd1 j16 bidirectional (optional: open-drain) general-purpose i/o port b bit 25?bit 25 of the general-purpose i/o port b. smtxd1?smc1 transmit data output. pb[24] smrxd1 j18 bidirectional (optional: open-drain) general-purpose i/o port b bit 24?bit 24 of the general-purpose i/o port b. smrxd1?smc1 receive data input. table 1. signal descriptions (continued) name reset number type description
21 TSPC860 [preliminary] 2129b?hirel?12/04 pb[23] smsyn1 sdack1 k17 bidirectional (optional: open-drain) general-purpose i/o port b bit 23?bit 23 of the general-purpose i/o port b. smsyn1 ?smc1 external sync input. sdack1 ?sdma acknowledge 1 output that is used as a peripheral interface signal for idma emulation, or as a cam interface signal for ethernet. pb[22] smsyn2 sdack2 l19 bidirectional (optional: open-drain) general-purpose i/o port b bit 22?bit 22 of the general-purpose i/o port b. smsyn2 ?smc2 external sync input. sdack2 ?sdma acknowledge 2 output that is used as a peripheral interface signal for idma emulation, or as a cam interface signal for ethernet. pb[21] smtxd2 l1clkob k16 bidirectional (optional: open-drain) general-purpose i/o port b bit 21?bit 21 of the general-purpose i/o port b. smtxd2?smc2 transmit data output. l1clkob?clock output from the serial interface tdm port b. pb[20] smrxd2 l1clkoa l16 bidirectional (optional: open-drain) general-purpose i/o port b bit 20?bit 20 of the general-purpose i/o port b. smrxd2?smc2 receive data input. l1clkoa?clock output from the serial interface tdm port a. pb[19] rts1 l1st1 n19 bidirectional (optional: open-drain) general-purpose i/o port b bit 19?bit 19 of the general-purpose i/o port b. rts1 ?request to send modem line for scc1. l1st1?one of four output strobes that can be generated by the serial interface. pb[18] rts2 l1st2 n17 bidirectional (optional: open-drain) general-purpose i/o port b bit 18?bit 18 of the general-purpose i/o port b. rts2 ?request to send modem line for scc2. l1st2?one of four output strobes that can be generated by the serial interface. pb[17] l1rqb l1st3 hi-z p18 bidirectional (optional: open-drain) general-purpose i/o port b bit 17?bit 17 of the general-purpose i/o port b. l1rqb ?d-channel request signal for the serial interface tdm port b. l1st3?one of four output strobes that can be generated by the serial interface. pb[16] l1rqa l1st4 n16 bidirectional (optional: open-drain) general-purpose i/o port b bit 16?bit 16 of the general-purpose i/o port b. l1rqa ?d-channel request signal for the serial interface tdm port a. l1st4?one of four output strobes that can be generated by the serial interface. pb[15] brgo3 r17 bidirectional general-purpose i/o port b bit 15?bit 15 of the general-purpose i/o port b. brgo3?brg3 output clock. table 1. signal descriptions (continued) name reset number type description
22 TSPC860 [preliminary] 2129b?hirel?12/04 pb[14] rstrt1 u18 bidirectional general-purpose i/o port b bit 14?bit 14 of the general-purpose i/o port b. rstrt1 ?scc1 serial cam interface outputs that marks the start of a frame. pc[15] dreq0 rts1 l1st1 d16 bidirectional general-purpose i/o port c bit 15?bit 15 of the general-purpose i/o port c. dreq0 ?idma channel 0 request input. rts1 ?request to send modem line for scc1. l1st1?one of four output strobes that can be generated by the serial interface. pc[14] dreq1 rts2 l1st2 d18 bidirectional general-purpose i/o port c bit 14?bit 14 of the general-purpose i/o port c. dreq1 ?idma channel 1 request input. rts2 ?request to send modem line for scc2. l1st2? one of four output strobes that can be generated by the serial interface. pc[13] l1rqb l1st3 e18 bidirectional general-purpose i/o port c bit 13?bit 13 of the general-purpose i/o port c. l1rqb ?d-channel request signal for the serial interface tdm port b. l1st3?one of four output strobes that can be generated by the serial interface. pc[12] l1rqa l1st4 f18 bidirectional general-purpose i/o port c bit 12?bit 12 of the general-purpose i/o port c. l1rqa ?d-channel request signal for the serial interface tdm port a. l1st4?one of four output strobes that can be generated by the serial interface. pc[11] cts1 j19 bidirectional general-purpose i/o port c bit 11?bit 11 of the general-purpose i/o port c. cts1 ?clear to send modem line for scc1. pc[10] cd1 tgate1 hi-z k19 bidirectional general-purpose i/o port c bit 10?bit 10 of the general-purpose i/o port c. cd1 ?carrier detect modem line for scc1. tgate1 ?timer 1/timer 2 gate signal. pc[9] cts2 l18 bidirectional general-purpose i/o port c bit 9?bit 9 of the general-purpose i/o port c. cts2 ?clear to send modem line for scc2. pc[8] cd2 tgate2 m18 bidirectional general-purpose i/o port c bit 8?bit 8 of the general-purpose i/o port c. cd2 ?carrier detect modem line for scc2. tgate2 ?timer 3/timer 4 gate signal. table 1. signal descriptions (continued) name reset number type description
23 TSPC860 [preliminary] 2129b?hirel?12/04 pc[7] cts3 l1tsyncb sdack2 m16 bidirectional general-purpose i/o port c bit 7?bit 7 of the general-purpose i/o port c. cts3 ?clear to send modem line for scc3. l1tsyncb?transmit sync input for the serial interface tdm port b. sdack2 ?sdma acknowledge 2 output that is used as a peripheral interface signal for idma emulation or as a cam interface signal for ethernet. pc[6] cd3 l1rsyncb r19 bidirectional general-purpose i/o port c bit 6?bit 6 of the general-purpose i/o port c. cd3 ?carrier detect modem line for scc3. l1rsyncb?receive sync input for the serial interface tdm port b. pc[5] cts4 l1tsynca sdack1 t18 bidirectional general-purpose i/o port c bit 5?bit 5 of the general-purpose i/o port c. cts4 ?clear to send modem line for scc4. l1tsynca?transmit sync input for the serial interface tdm port a. sdack1 ?sdma acknowledge 1output that is used as a peripheral interface signal for idma emulation or as a cam interface signal for ethernet. pc[4] cd4 l1rsynca t17 bidirectional general-purpose i/o port c bit 4?bit 4 of the general-purpose i/o port c. cd4 ?carrier detect modem line for scc4. l1rsynca?receive sync input for the serial interface tdm port a. pd[15] l1tsynca u17 bidirectional general-purpose i/o port d bit 15?bit 15 of the general-purpose i/o port d. l1tsynca?input transmit data sync signal to the tdm channel a. pd[14] l1rsynca v19 bidirectional general-purpose i/o port d bit 14?bit 14 of the general-purpose i/o port d. l1rsynca?input receive data sync signal to the tdm channel a. pd[13] l1tsyncb v18 bidirectional general-purpose i/o port d bit 13?bit 13 of the general-purpose i/o port d. l1tsyncb?input transmit data sync signal to the tdm channel b. pd[12] l1rsyncb hi-z r16 bidirectional general-purpose i/o port d bit 12?bit 12 of the general-purpose i/o port d. l1rsyncb?input receive data sync signal to the tdm channel b. pd[11] rxd3 t16 bidirectional general-purpose i/o port d bit 11?bit 11 of the general-purpose i/o port d. rxd3?receive data for serial channel 3. pd[10] txd3 w18 bidirectional general-purpose i/o port d bit 10?bit 10 of the general-purpose i/o port d. txd3?transmit data for serial channel 3. pd[9] rxd4 v17 bidirectional general-purpose i/o port d bit 9 ? bit 9 of the general-purpose i/o port d. rxd4?receive data for serial channel 4. pd[8] txd4 w17 bidirectional general-purpose i/o port d bit 8?bit 8 of the general-purpose i/o port d. txd4?transmit data for serial channel 4. table 1. signal descriptions (continued) name reset number type description
24 TSPC860 [preliminary] 2129b?hirel?12/04 pd[7] rts3 t15 bidirectional general-purpose i/o port d bit 7?bit 7 of the general-purpose i/o port d. rts3 ?active low request to send output indicates that scc3 is ready to transmit data. pd[6] rts4 v16 bidirectional general-purpose i/o port d bit 6?bit 6 of the general-purpose i/o port d. rts4 ?active low request to send output indicates that scc4 is ready to transmit data. pd[5] reject2 u15 bidirectional general-purpose i/o port d bit 5?bit 5 of the general-purpose i/o port d. reject2 ?this input to scc2 allows a cam to reject the current ethernet frame after it determines the frame address did not match. pd[4] reject3 u16 bidirectional general-purpose i/o port d bit 4?bit 4 of the general-purpose i/o port d. reject3 ?this input to scc3 allows a cam to reject the current ethernet frame after it determines the frame address did not match. pd[3] reject4 w16 bidirectional general-purpose i/o port d bit 3?bit 3 of the general-purpose i/o port d. reject4 ?this input to scc4 allows a cam to reject the current ethernet frame after it determines the frame address did not match. tck dsck hi-z (pulled up on rev 0 to rev a.3) h16 input provides clock to scan chain logic or for the development port logic. should be tied to vcc if jtag or development port are not used. tms pulled up g18 input controls the scan chain test mode operations. should be tied to power through a pull-up resistor if unused. tdi dsdi pulled up (hi- z on rev 0 to rev a.3) h17 input input serial data for either the scan chain logic or the development port and determines the operating mode of the development port at reset. tdo dsdo low g17 output output serial data for ei ther the scan chain logic or for the development port. trst pulled up g19 input reset for the scan chain logic. if jtag is not used, connect trst to ground. if jtag is used, connect trst to poreset . in case poreset logic is powered by the keep-alive power supply (kapwr), connect trst to poreset through a diode (anode connected to trst and cathode to poreset ). spare[1-4] hi-z b7, h18, v15, h4 no-connect spare signals?not used on current chip revisions. leave unconnected. power supply see figure 4 power v ddl ?power supply of the internal logic. v ddh ?power supply of the i/o buffers and certain parts of the clock control. v ddsyn ?power supply of the pll circuitry. kapwr?power supply of the internal oscm, rtc, pit, dec, and tb. v ss ?ground for circuits, except for the pll circuitry. v sssyn , v sssyn1 ?ground for the pll circuitry. table 1. signal descriptions (continued) name reset number type description
25 TSPC860 [preliminary] 2129b?hirel?12/04 active pull-up buffers active pull-up buffers are a special variety of bidirectional three-state buffer with the fol- lowing properties: when enabled as an output and driving low, they behave as normal output drivers (that is, the pin is constantly driven low). when enabled as an output and driving high, drive high until an internal detection circuit determines that the output has reached the logic high threshold and then stop driving (that is, the pin switches to high-impedance). when disabled as an output or functioning as an input, it should not be driven. due to the behavior of the buffer when being driven high, a pull-up resistor is required externally to function as a ?bus keep? for these shared signals in periods when no drivers are active and to keep the buffer from oscillating when the buffer is driving high, because if the voltage ever dips below the logic high threshold while the buffer is enabled as an output, the buff er will reactivate. furt her, external logi c must not attempt to drive these signals low while active pull-up buffers are enabled as outputs, because the buffers will reactivate and drive high, resulting in a buffer fight and possible damage to the TSPC860, to the system, or to both. figure 6 compares three-state buffers and active pull-up buffers graphically in general terms. it makes no implication as to which edges trigger which events for any particular signal. figure 6. three-state buffers and active pull-up buffers note: events 1 and 4 can be in quick succession. 1 2 3 12 3 5 4 1 drive high on one edge 2 switch to hi-z on later edge 3 pull-up resistor maintains logic high state 1 drive high on one edge 2 switch to hi-z when threshold voltage (voh + margin) is reached 3 pull-up resistor maintains logic high state 4 disable buffer as output 5 pull-up resistor maintains logic high state; other driver can drive signal three-state buffer active pull-up buffer
26 TSPC860 [preliminary] 2129b?hirel?12/04 table 2 summarizes when active pull-up drivers are enabled as outputs. the purpose of active pull-up buffers is to allow access to zero wait-state logic that drives a shared signal on the clock cycle immediately following a cycle in which the sig- nal is driven by the TSPC860. in other words, it eliminates the need for a bus turn- around cycle. internal pull-up and pull- down resistors the tms and trst pins have internal pull-up resistors. TSPC860 devices from rev 0 to rev a.3 (masks xe64c and xf84c) have an internal pull-up resistor on tck/dsck but no internal pull-up resistor on tdi/dsdi. this was corrected on rev b and later; on these chips, the internal pull-up resistor was removed from tck/dsck and an internal pull-up resistor was added to tdi/dsdi. if rstconf is pulled down, during hardwar e reset (initiated by hreset or pore- set ), the data bus d[0-31] is pulled down with internal pull-down resistors. these internal pull-down resistors are to provide a logic-zero default for these pins when pro- gramming the hard reset configuration word. these internal pull-down resistors are disconnected after hreset is negated. no other pins have internal pull-ups or pull-downs. resistance values for internal pull-up and pull-down resistors are not specified because their values may vary due to process variations and shrinks in die size, and they are not tested. typical values are on the order of 5 k ? but can vary by approximately a factor of 2. recommended basic pin connections reset configuration some external pin configuration is determi ned at reset by the hard reset configuration word. thus, some decisions as to system c onfiguration (for example, location of bdm pins) should be made before required application of pull-up and pull-down resistors can be determined. rstconf should be grounded if the hard reset configuration word is used to configure the TSPC860 or should be connected to v cc if the default configuration is used. pull-up resistors may not be used on d[0-31] to set the hard reset configuration word, as the values of the internal pull-down resistors are not specified or guaranteed. to change a data bus signal from its default logic low st ate during reset, actively drive that signal high. table 2. active pull-up resistors enabled as outputs signal description ts , bb when the TSPC860 is the external bu s master throughout the entire bus cycle. bi when the TSPC860?s memory controller responds to the access on the external bus, throughout the entire bus cycle. ta when the TSPC860?s memory controller responds to the access on the external bus, then: ? for chip-selects controlled by the gpcm set for external ta , the TSPC860?s ta buffer is not enabled as an output. ? for chip-selects controlled by the gpcm set to terminate in n wait-states, ta is enabled as an outp ut on cycle (n-1) and driven high, then is driven low on cycle n, terminating the bus transaction. external logic can drive ta at any point before this, thus terminating the cycle early. [for exam ple, assume the gpcm is programmed to drive ta after 15 cycles. if external logic drives ta before 14 clocks have elapsed then the ta will be accepted by the TSPC860 as a cycle termination.] ? for chip-selects controlled by the upm, the ta buffer is enabled as an output throughout the entire bus cycle.
27 TSPC860 [preliminary] 2129b?hirel?12/04 modck[1-2] must be used to determine the default clocking mode for the TSPC860. after hardware reset, the modck[1-2] pins change function and become outputs. thus, if these alternate functions are also desired, then the modck[1-2] configuration should be set with three-state drivers that turn off after hreset is negated; however, if modck[1-2] pins? alternate output functions are not used in the system, they can be configured with pull-up and pull-down resistors. signals with open-drain buffers and ac tive pull-up buffers (hreset , sreset , tea , ts , ta , bi , and bb ) must have external pull-up resistors. these signals include the following: some other input signals do not absolutely r equire a pull-up resistor, as they may be actively driven by external logic. however, if they are not used externally, or if the exter- nal logic connected to them is not always ac tively driving, they may need external pull- up resistors to hold them negated. these signals include the following: poreset as cr/irq3 kr/retry /irq4 /spkrout (if configured as kr /retry or irq4 ) any irqx (if configured as irqx ) br (if the TSPC860?s internal bus arbiter is used) bg (if an external bus arbiter is used) jtag and debug ports tck/dsck or ale_b/dsck/at1 (depending on the configuration of the dsck func- tion) should be connected to ground through a pull-down resistor to disable debug mode as a default. when required, a debug mode controller tool externally drives this signal high actively to put the TSPC860 into debug mode. two pins need special attention, depending on the version of TSPC860 used. for TSPC860 rev b and later, tdi/dsdi should be pulled up to v cc to keep it from oscillating when unused. for TSPC860 rev a.3 and earlier, tck/dsck should be connected to ground if it is configured for its dsck function, as stated above. however, for these versions of the TSPC860, the pull-down resistor must be strong (for example, 1 k ? to overcome the internal pull-up resistor. to allow application of any version of processor, perform both of the above actions. unused inputs in general, pull-up resistors should be used on any unused inputs to keep them from oscillating. for example, if pcmcia is not used, the pcmcia input pins (wait_a, wait_b, ip_a[0-8], ip_b[0-8]) should have external pull-up resistors. however, unused pins of port a, b, c, or d can be configured as outputs, and, if they are configured as outputs they do not require external terminations. unused outputs unused outputs can be left unterminated. signal states during hardware reset during hardware reset (hreset or poreset ), the signals of the TSPC860 behave as follows: the bus signals are high-impedance the port i/o signals are configured as inputs, and are therefore high-impedance the memory controller signals are driven to their inactive state
28 TSPC860 [preliminary] 2129b?hirel?12/04 however, some signal functions are determined by the reset configuration. when hreset is asserted, these signals immediately begin functioning as determined by the reset configuration and are either high-impedance or are drive to their inactive state accordingly. the behavior of these signals is shown in table 11. detailed specifications this specifications describes the specific requirements for the microcontroller TSPC860, in compliance with mil-std-883 class q or atmel standard screening. applicable documents 1. mil-std-883: test methods and procedures for electronics 2. mil-prf-38535 appendix a: general specifications for microcircuits the microcircuits are in accordance with the applicable documents and as specified herein. design and construction terminal connections the terminal connections shall be as shown in the general description. lead material and finish lead material and finish shall be as specified on page 87. table 3. signal states during hardware reset signal behavior bdip /gpl_b5 bdip : high impedance gpl_b5 : high rsv /irq2 rsv : high irq2 : high impedance kr /retry /irq4 /spkrout kr /retry /irq4 : high impedance spkrout: low frz/irq6 frz: low irq6 : high impedance ale_b/dsck/at1 ale_b: low dsck/at1: high impedance ip_b[0-1]/iwp[0-1]/vfls[0-1] ip_b[0-1]: high impedance iwp[0-1]: high vfls[0-1]: low ip_b3/iwp2/vf2 ip_b3: high impedance iwp2: high vf2: low ip_b4/lwp0/vf0 ip_b4: high impedance lwp0: high vf0: low ip_b5/lwp1/vf1 ip_b5: high impedance lwp1: high; vf1: low
29 TSPC860 [preliminary] 2129b?hirel?12/04 package the macrocircuits are packaged in 357-lead plastic ball grid array (bga) packages. the precise case outlines are described at the end of the specification. absolute maximum ratings stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. notes: 1. junction temperature is a function on on-chip power diss ipation, package thermal resistance, mounting site (board) temp er- ature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 wit h the single layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. boar d temperature is measured on the top surface of the board near the package. 5. indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperatur e used for the case temperature. for exposed pad packages where the pad would be expected to be soldered, junction to case thermal resistance is a simlated value from the junction to the exposed pas without contact resistance. 6. thermal characterization parameter indicating the temperature difference between package top and the junction tempera- ture per jedec jesd51-2. absolute maximum rating for the TSPC860 parameter symbol min max unit i/o supply voltage v ddh -0.3 4.0 v internal supply voltage v ddl -0.3 4.0 v backup supply voltage kapwr -0.3 4.0 v pll supply voltage v ddsyn -0.3 4.0 v input voltage v in -0.3 4.0 v storage temperature range t stg -65 +150 c table 4. thermal characteristics rating environnement symbol zp pc860p zq/vr pc860p unit junction to ambient (1) natural convection single layer board (1s) r ja (2) 34 34 c/w four layer board (2s2p) r jma (3) 22 22 air flow (200 ft/min) single layer board (1s) r jma (3) 27 27 four layer board (2s2p) r jma (3) 18 18 junction to board (4) r jb 14 13 junction to case (5) r jc 68 junction to package top (6) natural convection jt 22 air flow (20 ft/min) 2 3
30 TSPC860 [preliminary] 2129b?hirel?12/04 note: 1. typical power dissipation is measured at 3.3v 2. maximum power dissipation is measured at 3.5v 3. values in table 5 represent v ddl -based power dissipation and do not include i/o power dissipation over v ddh . i/o power dissipation varies widely by application due to buffer current, depending on external circuitry electrical characteristics general requirements all static and dynamic electrical characterist ics specified for inspection purposes and the relevant measurement conditions are given below. dc electrical specifications table 5. power dissipation (p d ) (3) die revision frequency typical (1) maximum (2) unit d.4 (1:1 mode) 50 656 735 mw 66 tbd tbd mw d.4 (2:1 mode) 66 722 762 mw 80 851 909 mw table 6. dc electrical specification with v cc = 3.3 5% v dc , gnd = 0 v dc , -55 c t c 125 c characteristic symbol min max unit operating voltage v ddh , v ddl , kapwr, v ddsyn 3.135 3.465 v kapwr (power-down mode) 2.0 3.6 v kapwr (all other operating modes) v ddh - 0.4 v ddh v input high voltage (all inputs except extal and extclk) v ih 2.0 5.5 v input low voltage v il gnd 0.8 v extal, extclk inpu t high voltage v ihc 0.7 (v ddh )v ddh + 0.3 v input leakage current, v in = 5.5v (except tms, trst, dsck and dsdi pins) i in - 100 a input leakage current, v in = 3.6v (except tms, trst , dsck and dsdi pins) i in -10a input leakage current, v in = 0v (except tms, trst , dsck and dsdi pins) i in -10a output high voltage, i oh = -2.0 ma, v ddh = 3.0v except xtal, xfc, and open drain pins voh 2.4 - v
31 TSPC860 [preliminary] 2129b?hirel?12/04 notes: 1. vil(max) for the i 2 c interface is 0.8v rather than the 1.5v as specified in the i 2 c standard. 2. input capacitance is periodically sampled. output low voltage vol - 0.5 v iol = 2.0 ma clkout iol = 3.2 ma a(0:31), tsiz0/reg, tsiz 1, d(0:31), dp(0:3)/irq (3:6), rd/wr , burst , rsv/irq2 , ip_b(0:1)/iwp(0:1)/vfls(0:1), ip_b2/iois16_b/at2, ip_b3/iwp2/vf2, ip_b4/lwp0/vf0, ip_b5/lwp1/vf1, ip_b6/dsdi/at0, ip_b7/ptr/at3, rxd1 /pa15, rxd2/pa13, l1txdb/pa11, l1rxdb/pa10, l1txda/pa9, l1rxda/pa8, tin1/l1rclka/brgo1/clk1/pa7, brgclk1/tout1 /clk2/pa6, tin2/l1tclka/brgo2/clk3/pa5, tout2 /clk4/pa4, tin3/brgo3/clk5/pa3, brgclk2/l1rclkb/tout3 /clk6/pa2, tin4/brgo4/clk7/pa1, l1tclkb/tout4 /clk8/pa0, rrjct1/spisel/pb31, spiclk /pb30, spimosi/pb29, brgo4/spimiso/pb28, brgo1/i2csda/pb27, brgo2/i2cscl/pb26, smtxd1/pb25, smrxd1/pb24, smsyn1/sdack1/pb23, smsyn2/sdack2/pb22, sm txd2/l1clkob/pb21, smrxd2/l1clkoa/pb20, l1st1/rts1/pb19, l1st2/rts2/pb18, l1st3/l1rqb/pb17, l1st4/l1rqa/pb16, brgo3/pb15, rstrt1 /pb14, l1st1/rts1/dreq0/pc15, l1st2/rts2/dreq1/pc14, l1st3/l1rqb/pc13, l1st4/l1rqa/pc12, cts1/p c11, tgate1/cd1/pc10, cts2/pc9, tgate2/cd2/pc8, cts3 /sdack2/l1tsyncb/pc7, cd3 /l1rsyncb/pc6, cts4 /sdack1/l1tsynca/pc5, cd4 /l1rsynca/pc4, pd15/l1tsynca, pd14/l1rsynca, pd13/l1tsyncb, pd12/l1rsyncb, pd11/rxd3, pd10/txd3, pd9/rxd4, pd8/txd4, pd5/rrjct2, pd6/rts4 , pd7/rts3, pd4 /rrjct3, pd3 iol = 5.3 ma bdip /gpl_b(5), br , bg , frz/irq6, cs (0:5), cs (6)/ce (1)_b, cs (7)/ce (2)_b, we0 /bs _b0/iord , we1 /bs _b1/iowr , we2 /bs _b2/pcoe , we3 /bs _b3/pcwe , bs _a(0:3), gpl_a0/gpl_b0, oe /gpl_a1/gpl_b1, gpl_ a(2:3)/gpl_b(2:3)/cs (2:3), upwaita/gpl_a4, upwaitb/gpl_b4, gpl_a5, ale_a, ce 1_a, ce 2_a, ale_b/dsck/at1, op(0:1), op2/modck1/sts , op3/modck2/dsdo, baddr(28:30) iol = 7.0 ma txd1/pa14, txd2/pa12 iol = 8.9 ma ts , ta , tea , bi , bb , hreset , sreset input capacitance cin - 20 pf table 6. dc electrical specification with v cc = 3.3 5% v dc , gnd = 0 v dc , -55 c t c 125 c (continued) characteristic symbol min max unit
32 TSPC860 [preliminary] 2129b?hirel?12/04 ac electrical specifications control timing figure 7. ac electrical specificat ions control timing diagram the timing for the TSPC860 bus shown assumes a 50 pf load for maximum delays and a 0 pf load for minimum delays. for loads other than 50 pf, maximum delays can be derated by 1 ns per 10 pf. clkout outputs inputs inputs 2.0v 0.8v 2.0v 2.0v 0.8v 0.8v 2.0v 2.0v 0.8v 0.8v 2.0v 2.0v 0.8v 0.8v 2.0v a b cd a. maxi mu m output delay speci ficat ion b. minim um out put hold time c. minim um input setup time specification d. minim um input hold time specification outputs 2.0v 0.8v 0.8v 2.0v a b 0.8v cd
33 TSPC860 [preliminary] 2129b?hirel?12/04 table 7. bus operation timings num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max b1 clkout period 30.30 30.30 25 30.30 20 30.30 15.15 30.30 ns b1a extclk to clkout phase skew (extclk > 15 mhz and mf 2) -0.90 0.90 -0.90 0.90 -0.90 0.90 -0.90 0.90 ns b1b extclk to clkout phase skew (extclk > 10 mhz and mf < 10) -2.30 2.30 -2.30 2.30 -2.30 2.30 -2.30 2.30 ns b1c clkout phase jitter (extclk > 15 mhz and mf 2) (1) -0.60 0.60 -0.60 0.60 -0.60 0.60 -0.60 0.60 ns b1d clkout phase jitter -2 2 -2 2 -2 2 -2 2 ns b1e clkout frequency jitter (mf < 10) ? 0.50 ? 0.50 ? 0.50 ? 0.50 % b1fclkout frequency jitter (10 < mf < 500) ?2?2?2?2% b1g clkout frequency jitter (mf > 500) ? 3?3?3?3% b1h frequency jitter on extclk (2) ?0.50?0.50?0.50?0.50% b2 clkout pulse width low 12.12 ? 10 ? 8 ? 6.06 ? ns b3 clkout width high 12.12 ? 10 ? 8 ? 6.06 ? ns b4 clkout rise time (3) ?4?4?4?4ns b5 clkout fall time (3) ?4?4?4?4ns b7 clkout to a(0:31), baddr(28:30), rd/wr , burst , d(0:31), dp(0:3) invalid 7.58 ? 6.25 ? 5 ? 3.80 ? ns b7a clkout to tsiz(0:1), reg , rsv , at(0:3), bdip , ptr invalid 7.58 ? 6.25 ? 5 ? 3.80 ? ns b7b clkout to br , bg , frz, vfls(0:1), vf(0:2), iwp(0:2), lwp(0:1), sts invalid (4) 7.58 ? 6.25 ? 5 ? 3.80 ? ns b8 clkout to a(0:31), baddr(28:30), rd/wr , burst , d(0:31), dp(0:3) valid 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns b8a clkout to tsiz(0:1), reg , rsv , at(0:3), bdip , ptr valid 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns b8b clkout to br , bg , vfls(0:1), vf(0:2), iwp(0:2), frz, lwp(0:1), sts valid (4) 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns b9 clkout to a(0:31), baddr(28:30), rd/wr , burst , d(0:31), dp(0:3), tsiz(0:1), reg , rsv , at(0:3), ptr high z 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns b11 clkout to ts , bb assertion 7.58 13.58 6.25 12.25 5 11 3.80 11.29 ns b11a clkout to ta , bi assertion (when driven by the memory controller or pcmcia i/f) 2.50 9.25 2.50 9.25 2.50 9.25 2.50 9.75 ns b12 clkout to ts , bb negation 7.58 14.33 6.25 13 5 11.75 3.80 8.54 ns b12a clkout to ta , bi negation (when driven by the memory controller or pcmcia interface) 2.50 11 2.50 11 2.50 11 2.50 9 ns b13 clkout to ts , bb high z 7.58 21.58 6.25 20.25 5 19 3.80 14.04 ns
34 TSPC860 [preliminary] 2129b?hirel?12/04 b13a clkout to ta , bi high z (when driven by the memory controller or pcmcia interface) 2.50 15 2.50 15 2.50 15 2.50 15 ns b14 clkout to tea assertion 2.50102.50102.50102.50 9 ns b15 clkout to tea high z 2.50152.50152.50152.5015 ns b16 ta , bi valid to clkout (setup time) 9.75 ? 9.75 ? 9.75 ? 6 ? ns b16a tea , kr , retry , cr valid to clkout (setup time) 10 ? 10 ? 10 ? 4.50 ? ns b16b bb , bg , br , valid to clkout (setup time) (5) 8.50?8.50?8.50? 4 ? ns b17 clkout to ta , tea , bi , bb , bg , br valid (hold time) 1?1?1?2?ns b17a clkout to kr , retry , cr valid (hold time)2?2?2?2?ns b18 d(0:31), dp(0:3) valid to clkout rising edge (setup time) (6) 6?6?6?6?ns b19 clkout rising edge to d(0:31), dp(0:3) valid (hold time) (6) 1?1?1?2?ns b20 d(0:31), dp(0:3) valid to clkout falling edge (setup time) (7) 4?4?4?4?ns b21 clkout falling edge to d(0:31), dp(0:3) valid (hold time) (7) 2?2?2?2?ns b22 clkout rising edge to cs asserted -gpcm- acs = 00 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns b22a clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf = 0 ?8?8?8?8ns b22b clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf = 0 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns b22c clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf = 1 10.86 17.99 8.88 16 7 14.13 5.18 12.31 ns b23 clkout rising edge to cs negated -gpcm- read access, -gpcm- write access, acs = ?00?, trlx = ?0? & csnt = ?0? 28282822ns b24 a(0:31) and baddr(28:30) to cs asserted -gpcm- acs = 10, trlx = 0 5.58 ? 4.25 ? 3 ? 1.79 ? ns b24a a(0:31) and baddr(28:30) to cs asserted -gpcm- acs = 11, trlx = 0 13.15 ? 10.5 ? 8 ? 5.58 ? ns b25 clkout rising edge to oe ,we (0:3) asserted ?9?9?9?9ns b26 clkout rising edge to oe negated 29292929ns b27 a(0:31) and baddr(28:30) to cs asserted -gpcm- acs = 10, trlx = 1 35.88 ? 29.25 ? 23 ? 16.94 ? ns b27a a(0:31) and baddr(28:30) to cs asserted -gpcm- acs = 11, trlx = 1 43.45 ? 35.50 ? 28 ? 20.73 ? ns table 7. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
35 TSPC860 [preliminary] 2129b?hirel?12/04 b28 clkout rising edge to we (0:3) negated gpcm write access csnt = 0 ?9?9?9?9ns b28a clkout falling edge to we (0:3) negated -gpcm- write access trlx = 0, csnt = 1, ebdf = 0 7.58 14.33 6.25 13 5 11.75 3.8 10.54 ns b28b clkout falling edge to cs negated -gpcm- write access trlx = ?0?, csnt = ?1?, acs = 11, ebdf = 0 ? 14.33 ? 13 ? 11.75 ? 10.54 ns b28c clkout falling edge to we (0:3) negated -gpcm- write access trlx = ?0?, csnt = ?1? write access trlx = 0, csnt = 1, ebdf = 1 10.86 17.99 8.88 16 7 14.13 5.18 12.31 ns b28d clkout falling edge to cs negated -gpcm- write access trlx = ?0?, csnt = ?1?, acs = 10, or acs = ?11?, ebdf = 1 ? 17.99 ? 16 ? 14.13 ? 12.31 ns b29 we (0:3) negated to dp (0:3) high-z -gpcm- write access, csnt = 0, ebdf = 0 5.58 ? 4.25 ? 3 ? 1.79 ? ns b29a we (0:3) negated to d(0:31), dp(0:3) high z -gpcm- write access, trlx = ?0?, csnt = 1?, ebdf = 0 13.15 ? 10.5 ? 8 ? 5.58 ? ns b29b cs negated to d(0:31), dp(0:3) high z -gpcm- write access, acs = ?00?, trlx = ?0? & csnt = ?0? 5.58 ? 4.25 ? 3 ? 1.79 ? ns b29c cs negated to d(0:31), dp(0:3) high z -gpcm- write access, trlx = ?0?, csnt = ?1?, acs = ?11,?, ebdf = 0 13.15 ? 10.5 ? 8 ? 5.58 ? ns b29d we (0:3) negated to d(0:31), dp(0:3) high z -gpcm- write access, trlx = ?1?, csnt = ?1?, ebdf = 0 43.45 ? 35.5 ? 28 -? 20.73 ? ns b29e cs negated to d (0:31), dp(0:3) high z -gpcm- write access, trlx = 1, csnt = 1, acs = 10, or acs = 11 ebdf = 0 43.45 ? 35.5 ? 28 ? 29.73 ? ns b29f we (0:3) negated to d(0:31), dp(0:3) high z -gpcm- write access, trlx = ?0?, csnt = ?1?, ebdf = 1 8.86 ? 6.8 ? 5 ? 3.48 ? ns b29g cs negated to d(0:31), dp(0:3) high z -gpcm- write access, trlx = ?0?, csnt = ?1?, acs = ?10? or acs = ?11?, ebdf = 1 8.86 ? 6.8 ? 5 ? 3.48 ? ns b29h we (0:3) negated to d(0:31), dp(0:3) high z -gpcm- write access, trlx = ?1?, csnt = ?1?, ebdf = 1 38.67 ? 31.38 ? 24.50 ? 17.83 ? ns b29i cs negated to d(0:31), dp(0:3) high z -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = ?10? or acs = ?11 ?, ebdf = 1 38.67 ? 31.38 ? 24.50 ? 17.83 ? ns b30 cs , we (0:3) negated to a(0:31), baddr(28:30) invalid -gpcm- write access (8) 5.58 ? 4.25 ? 3 ? 1.79 ? table 7. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
36 TSPC860 [preliminary] 2129b?hirel?12/04 b30a we (0:3) negated to a(0:31), baddr(28:30) invalid -gpcm- write access, trlx = ?0?, csnt = ?1?. cs negated to a(0:31) invalid gpcm write access, trlx = ?0?, csnt = ?1?, acs = 10, acs = 11, ebdf = 0 13.15 ? 10.50 ? 8 ? 5.58 ? ns b30b we (0:3) negated to a(0:31), baddr(28:30) invalid -gpcm- write access, trlx = ?1?, csnt = ?1?. cs negated to a(0:31) invalid -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = 10, acs = ?1 1?, ebdf = 0 43.45 ? 35.50 ? 28 ? 20.73 ? ns b30c we (0:3) negated to a(0:31), baddr(28:30) invalid -gpcm- write access, trlx = ?0?, csnt = ?1?. cs negated to a(0:31) invalid -gpcm- write access, trlx = ?0?, csnt = ?1?, acs=10, acs= ?11?, ebdf=1 8.36?6.38?4.50?2.68? ns b30d we (0:3) negated to a(0:31), baddr(28:30) invalid -gpcm- write access, trlx = ?1?, csnt = ?1?. cs negated to a(0:31) invalid -gpcm- write access, trlx = ?1?, csnt = ?1?, acs = 10,acs = ?11?, ebdf = 1 38.67 ? 31.38 ? 24.50 ? 17.83 ? ns b31 clkout falling edge to cs valid - as requested by control bit cst4 in the corresponding word in the upm 1.5 6 1.50 6 1.50 6 1.50 6 ns b31a clkout falling edge to cs valid - as requested by control bit cst1 in the corresponding word in the upm 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns b31b clkout rising edge to cs valid - as requested by control bit cst2 in the corresponding word in the upm 1.5081.5081.5081.508 ns b31c clkout rising edge to cs valid - as requested by control bit cst3 in the corresponding word in the upm 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns b31d clkout falling edge to cs valid - as requested by control bit cst1 in the corresponding word in the upm, ebdf = 1 13.26 17.99 11.28 16 9.40 14.13 7.58 12.31 ns b32 clkout falling edge to bs valid - as requested by control bit bst4 in the corresponding word in the upm 1.5061.5061.5061.506 ns b32a clkout falling edge to bs valid - as requested by control bit bst1 in the corresponding word in the upm, ebdf = 0 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns table 7. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
37 TSPC860 [preliminary] 2129b?hirel?12/04 b32b clkout rising edge to bs valid - as requested by control bit bst2 in the corresponding word in the upm 1.5081.5081.5081.508 ns b32c clkout rising edge to bs valid - as requested by control bit bst3 in the corresponding word in the upm 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns b32d clkout falling edge to bs valid - as requested by control bit bst1 in the corresponding word in the upm, ebdf = 1 13.26 17.99 11.28 16 9.40 14.13 7.58 12.31 ns b33 clkout falling edge to gpl valid - as requested by control bit gxt4 in the corresponding word in the upm 1.5061.5061.5061.506 ns b33a clkout rising edge to gpl valid - as requested by control bit gxt3 in the corresponding word in the upm 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns b34 a(0:31), baddr(28:30), and d(0:31) to cs valid as requested by control bit cst4 in the corresponding word in the upm 5.58 ? 4.25 ? 3 ? 1.79 ? ns b34a a(0:31), baddr(28:30), and d(0:31) to cs valid as requested by control bit cst1 in the corresponding word in the upm 13.15 ? 10.50 ? 8 ? 5.58 ? ns b34b a(0:31), baddr(28:30), and d(0:31) to cs valid as requested by control bit cst2 in the corresponding word in the upm 20.73 ? 16.75 ? 13 ? 9.36 ? ns b35 a(0:31), baddr(28:30), and d(0:31) to bs valid as requested by control bit bst4 in the corresponding word in the upm 5.58 ? 4.25 ? 3 ? 1.79 ? ns b35a a(0:31), baddr(28:30), and d(0:31) to bs valid as requested by control bit bst1 in the corresponding word in the upm 13.15 ? 10.50 ? 8 ? 5.58 ? ns b35b a(0:31), baddr(28:30), and d(0:31) to bs valid as requested by control bit bst2 in the corresponding word in the upm 20.73 ? 16.75 ? 13 ? 9.36 ? ns b36 a(0:31), baddr(28:30), and d(0:31) to gpl valid as requested by control bit gxt4 in the corresponding word in the upm 5.58 ? 4.25 ? 3 ? 1.79 ? ns b37 upwait valid to clkout falling edge (9) 6?6?6?6?ns b38 clkout falling edge to upwait valid (9) 1?1?1?1?ns b39 as valid to clkout rising edge (10) 7?7?7?7?ns b40 a(0:31), tsiz(0:1), rd/wr , burst , valid to clkout rising edge. 7?7?7?7?ns table 7. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max
38 TSPC860 [preliminary] 2129b?hirel?12/04 notes: 1. phase and frequency jitter performance results are only va lid if the input jitter is less than the prescribed value. 2. if the rate of change of the frequency of extal is slow (i .e. it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e. it does not stay at an extreme value for a long time) then the maximum allowed jitter on extal can be up to 2% 3. the timings specified in b4 and b5 are based on full strength clock. 4. the timing for br output is relevant when the pc860 is selected to wo rk with the external bus arbiter. the timing for bg out- put is relevant when the pc860 is selected to work with internal bus arbiter. 5. the timing required for br input is relevant when the TSPC860 is selected to work with internal bus arbiter. the timing for bg input is relevant when the TSPC860 is selected to work with internal bus arbiter. 6. the d (0:31) and dp (0:3) input timings b20 and b21 refer to the rising edge of the clkout in which the ta input signal is asserted. 7. the d (0:31) and dp (0:3) input timings b20 and b21 refer to the falling edge of the clkout. this timing is valid only for read accesses controlled by chip-selects under control of t he upm in the memory controller, for data beats where dlt3 = 1 in the upm ram words. (this is only the cases where data is latched on the falling edge of clkout). 8. the timing b30 refers to cs when acs = 00 and to we (0:3) when csnt = 0 9. the signal upwait is considered asynchronous to the clko ut and synchronized internally. the timings specified in b37 and b38 are specified to enable the freeze of t he upm output signals as described in figure 22. 10. the as signal is considered asynchronous to the clkout. the timi ng b39 is specified in order to allow the behavior speci- fied in figure 25. figure 8. external clock timing b41 ts valid to clkout rising edge (setup time).7?7?7?7?ns b42clkout rising edge to ts valid (hold time).2?2?2?2?ns b43 as negation to memory controller signals negation ? tbd ? tbd ? tbd ? tbd ns table 7. bus operation timings (continued) num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max clkout b1 b5 b3 b4 b1 b2
39 TSPC860 [preliminary] 2129b?hirel?12/04 figure 9. synchronous output signals timing figure 10. synchronous active pull-up and open drain output signals timing clkout output signals output signals output signals b8 b7 b9 b8a b9 b7a b8b b7b clkout ts , bb ta , bi tea b13 b12 b11 b11a b12a b13a b15 b14
40 TSPC860 [preliminary] 2129b?hirel?12/04 figure 11. synchronous input signals timing figure 12. input data timing in normal case figure 13. input data timing when controlled by upm in the memory controller clkout ta , bi tea , kr , retry , cr bb , bg , br b16 b17 b16a b17a b16b b17 clkout ta d[0:31], dp[0:3] b16 b17 b19 b18 clkout ta d[0:31], dp[0:3] b20 b21
41 TSPC860 [preliminary] 2129b?hirel?12/04 figure 14. external bus read timing (gpcm controlled ? acs = ?00?) clkout a[0:31] cs x oe we [0:3] ts d[0:31], dp[0:3] b11 b12 b23 b8 b22 b26 b19 b18 b25 b28
42 TSPC860 [preliminary] 2129b?hirel?12/04 figure 15. external bus read timing (gpcm controlled ? trlx = ?0? acs = ?10?) figure 16. external bus read timing (gpcm controlled ? trlx = ?0? acs = ?11?) clkout a[0:31] cs x oe ts d[0:31], dp[0:3] b11 b12 b8 b22a b23 b26 b19 b18 b25 b24 clkout a[0:31] cs x oe ts d[0:31], dp[0:3] b11 b12 b22b b8 b22c b23 b24a b25 b26 b19 b18
43 TSPC860 [preliminary] 2129b?hirel?12/04 figure 17. external bus read timing (gpcm controlled ? trlx = ?1?, acs = ?10?, acs = ?11?) clkout a[0:31] cs x oe ts d[0:31], dp[0:3] b11 b12 b8 b22a b27 b27a b22b b22c b19 b18 b26 b23
44 TSPC860 [preliminary] 2129b?hirel?12/04 figure 18. external bus write timing (gpcm cont rolled ? trlx = ?0?, csnt = ?0?) clkout a[0:31] cs x we [0:3] oe ts d[0:31], dp[0:3] b11 b8 b22 b23 b12 b30 b28 b25 b26 b8 b9 b29 b29b
45 TSPC860 [preliminary] 2129b?hirel?12/04 figure 19. external bus write timing (gpcm controlled ? trlx = ?0?, csnt = ?1?) b23 b30a b30c clkout a[0:31] cs x oe we [0:3] ts d[0:31], dp[0:3] b11 b8 b22 b12 b28b b28d b25 b26 b8 b28a b9 b28c b29c b29g b29a b29f
46 TSPC860 [preliminary] 2129b?hirel?12/04 figure 20. external bus write timing (gpcm controlled ? trlx = ?1?, csnt = ?1?) b23 b22 b8 b12 b11 clkout a[0:31] cs x we [0:3] ts oe d[0:31], dp[0:3] b30d b30b b28b b28d b25 b29e b29i b26 b29d b29h b28a b28c b9 b8 b29b
47 TSPC860 [preliminary] 2129b?hirel?12/04 figure 21. external bus timing (upm controlled signals) figure 22. asynchronous upwait asserted detection in upm handled cycles timing clkout cs x b31d b8 b31 b34 b32b gpl_a [0:5], gpl_b [0:5] bs_a [0:3], bs_b [0:3] a[0:31] b31c b31b b34a b32 b32a b32d b34b b36 b35b b35a b35 b33 b32c b33a b31a clko ut cs x upwait gpl_ a[0:5], gp l_b [0:5 ] bs_a[0:3], bs_b [0:3 ] b37 b38
48 TSPC860 [preliminary] 2129b?hirel?12/04 figure 23. asynchronous upwait negated detection in upm handled cycles timing figure 24. synchronous external master access timing ? gpcm handled acs = ?00? cl kout cs x upwait gpl_ a [0:5], gpl_ b[0 :5] bs _a[0:3], bs_b [0 :3] b37 b38 cl kout ts a[0:31], tsiz[0:1], r/w , burst cs x b41 b42 b40 b22
49 TSPC860 [preliminary] 2129b?hirel?12/04 figure 25. asynchronous external master memory access timing (gpcm controlled ? acs = ?00?) figure 26. asynchronous external master ? control signals negation time notes: 1. the timings i39 and i40 describe th e testing conditions under which the irq lines are tested when being defined as level sensitive. the irq lines are synchronized internally and do not have to be asserted or negated with reference to the clk- out. the timings i41, i42 and i43 are specified to allow the correct function of the irq lines detection circuitry, and has no direct relation with the total system interrupt lat ency that the TSPC860 is able to support. cl kout as a[0:31], tsiz[0:1], r/ w cs x b39 b40 b22 as b43 csx, we[0:3], oe, gplx, bs[0:3] table 8. interrupt timing number characteristic (1) all frequencies unit min max i39 irq x valid to clkout rising edge (set up time) 6 ? ns i40 irq x hold time after clkout 2 ? ns i41 irq x pulse width low 3 ? ns i42 irq x pulse width high 3 ? ns i43 irq x edge to edge time 4 t clockout ??
50 TSPC860 [preliminary] 2129b?hirel?12/04 figure 27. interrupt detection timing for external level sensitive lines figure 28. interrupt detection timing for external edge sensitive lines notes: 1. psst = 1. otherwise add psst times cycle time. 2. psht = 1. otherwise add psht times cycle time. clkout irq x i39 i40 clkout irq x i41 i42 i43 i43 table 9. pcmcia timing num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max p44 a(0:31), reg valid to pcmcia strobe asserted (1) 20.73 ? 16.75 ? 13 ? 9.36 ? ns p45 a(0:31), reg valid to ale negation (1) 28.30 ? 23 ? 18 ? 13.15 ? ns p46 clkout to reg valid 7.58 15.58 6.25 14.25 5 13 3.79 11.84 ns p47 clkout to reg invalid 8.58 ? 7.25 ? 6 ? 4.84 ? ns p48 clkout to ce 1, ce 2 asserted 7.58 15.58 6.25 14.25 5 13 3.79 11.84 p49 clkout to ce 1, ce 2 negated 7.58 15.58 6.25 14.25 5 13 3.79 11.84 ns p50 clkout to pcoe , iord , pcwe , iowr assert time 11 11 ns p51 clkout to pcoe , iord , pcwe , iowr negate time 211211 ns p52 clkout to ale assert time 7.58 15.58 6.25 14.25 5 13 3.79 11.04 ns p53 clkout to ale negate time ? 15.58 ? 14.25 ? 13 ? 11.84 ns p54 pcwe , iowr negated to d(0:31) invalid (1) 5.58 ? 4.25 ? 3 ? 1.79 ? ns p55 waita and waitb valid to clkout rising edge (1) 8 ? 8 ? 8 ? 8 ? ns p56 clkout rising edge to waita and waitb invalid (1) 2 ? 2 ? 2 ? 2 ? ns
51 TSPC860 [preliminary] 2129b?hirel?12/04 these synchronous timings define when the waitx signals are detected in order to freeze (or relieve) the pcmcia current cycle. the waitx assertion will be effective only if it is de tected 2 cycles before the psl timer expiration. figure 29. pcmcia access cycles timing external bus read cl kout a[0:31 ] reg ce1 /ce2 pcoe, io rd ts d[0:31] al e b19 b1 8 p53 p52 p52 p5 1 p50 p48 p49 p46 p45 p4 4 p47
52 TSPC860 [preliminary] 2129b?hirel?12/04 figure 30. pcmcia access cycles timing external bus write figure 31. pcmcia wait signals detection timing note: 1. op2 and op3 only. clkout a[0:31] reg ce1 /ce2 pcwe, iowr ts d[0:31] ale b9 b8 p53 p52 p52 p51 p50 p48 p49 p46 p45 p44 p47 p54 clkout wai t x p55 p56 table 10. pcmcia port timing num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max p57 clkout to opx valid ? 19 ? 19 ? 19 ? 19 ns p58 hreset negated to opx drive (1) 25.73 ? 21.75 ? 18 ? 14.36 ? ns p59 ip_xx valid to clkout rising edge 5 ? 5 ? 5 ? 5 ? ns p60 clkout rising edge to ip_xx invalid 1 ? 1 ? 1 ? 1 ? ns
53 TSPC860 [preliminary] 2129b?hirel?12/04 figure 32. pcmcia output port timing figure 33. pcmcia input port timing clkout hreset outpu t signals op2, op3 p57 p58 cl kout input signals p59 p60 table 11. debug port timing num characteristic all frequencies unit min max p61 dsck cycle time 3 t clockout ?? p62 dsck clock pulse width 1.25 t clockout ?? p63 dsck rise and fall times 0 3 ns p64 dsdi input data setup time 8 ? ns p65 dsdi data hold time 5 ? ns p66 dsck low to dsdo data valid 0 15 ns p67 dsck low to dsdo invalid 0 2 ns
54 TSPC860 [preliminary] 2129b?hirel?12/04 figure 34. debug port clock input timing figure 35. debug port timings cl kout input signals p59 p60 dsck dsdi dsdo d64 d65 d66 d67
55 TSPC860 [preliminary] 2129b?hirel?12/04 figure 36. reset timing ? configuration from data bus table 12. reset timing num characteristic 33 mhz 40 mhz 50 mhz 66 mhz unit min max min max min max min max r69 clkout to hreset high impedance ? 20 ? 20 ? 20 ? 20 ns r70 clkout to sreset high impedance ? 20 ? 20 ? 20 ? 20 ns r71 rstconf pulse width 515.15 ? 425 340 ? 257.58 ? ns r72 ? ? ? ??????? r73 configuration data to hreset rising edge set up time 504.55 ? 425 ? 350 ? 277.27 ? ns r74 configuration data to rstconf rising edge set up time 350 ? 350 ? 350 ? 350 ? ns r75 configuration data hold time after rstconf negation 0 ? 0?0?0?ns r76 configuration data hold time after hreset negation 0 ? 0?0?0?ns r77 hreset and rstconf asserted to data out drive ? 25 ?25?25?25ns r78 rstconf negated to data out high impedance. ? 25 ?25?25?25ns r79 clkout of last rising edge before chip tristates hreset to data out high impedance. ? 25 ?25?25?25ns r80 dsdi, dsck set up 90.91 ? 75 ? 60 ? 45.45 ? ns r81dsdi, dsck hold time 0 ? 0?0?0?ns r82 sreset negated to clkout rising edge for dsdi and dsck sample 242.42 ? 200 ? 160 ? 121.21 ? ns hreset rstcon f d[0:31] (i n) r71 r74 r73 r75 r76
56 TSPC860 [preliminary] 2129b?hirel?12/04 figure 37. reset timing ? TSPC860 data bus weak drive during configuration figure 38. reset timing ? debug port configur ation ieee 1149.1 electr ical specifications clko ut hreset d[0:31] (out ) (weak) rstcon f r69 r79 r77 r78 clkout sreset dsck, dsdi r70 r82 r80 r80 r81 r81
57 TSPC860 [preliminary] 2129b?hirel?12/04 figure 39. jtag test clock input timing figure 40. jtag ? test access port timing diagram table 13. jtag timing num characteristic all frequencies unit min max j82 tck cycle time 100 ? ns j83 tck clock pulse width measured at 1.5v 40 ? ns j84 tck rise and fall times 0 10 ns j85 tms, tdi data setup time 5 ? ns j86 tms, tdi data hold time 25 ? ns j87 tck low to tdo data valid ? 27 ns j88 tck low to tdo data invalid 0 ? ns j89 tck low to tdo high impedance ? 20 ns j90 trst assert time 100 ? ns j91 trst setup time to tck low 40 ? ns j92 tck falling edge to output valid ? 50 ns j93 tck falling edge to output valid out of high impedance ? 50 ns j94 tck falling edge to output high impedance ? 50 ns j95 boundary scan input valid to tck rising edge 50 ? ns j96 tck rising edge to boundary scan input invalid 50 ? ns tck j82 j83 j82 j83 j84 j84 tck tms, tdi tdo j85 j86 j87 j88 j89
58 TSPC860 [preliminary] 2129b?hirel?12/04 figure 41. jtag ? trst timing diagram figure 42. boundary scan (jtag) timing diagram tck trst j91 j90 tck output signals output signals output signals j92 j94 j93 j95 j96
59 TSPC860 [preliminary] 2129b?hirel?12/04 cpm electrical characteristics pip/pio ac electri cal specifications note: 1. t3 = specification 23 figure 43. pip rx (interlock mode) timing diagram table 14. pip/pio timing num characteristic all frequencies unit min max 21 data-in setup time to stbi low 0 ? ns 22 data-in hold time to stbi high 2.5 - t3 (1) ?clk 23 stbi pulse width 1.5 ? clk 24 stbo pulse width 1 clk - 5 ns ? ns 25 data-out setup time to stbo low 2 ? clk 26 data-out hold time from stbo high 5 ? clk 27 stbi low to stbo low (rx interlock) ? 2 clk 28 stbi low to stbo high (tx interlock) 2 ? clk 29 data-in setup time to clock low 15 ? ns 30 data-in hold time from clock low 7.5 ? ns 31 clock high to data-out valid (cpu writ es data, control, or direction) ? 25 ns 21 23 24 22 data in 27 stbi stbo
60 TSPC860 [preliminary] 2129b?hirel?12/04 figure 44. pip tx (interlock mode) timing diagram figure 45. pip rx (pulse mode) timing diagram 25 23 28 24 26 data out stbo (output) stbi (input) 21 22 23 24 data in stbi (input) stbo (output)
61 TSPC860 [preliminary] 2129b?hirel?12/04 figure 46. pip tx (pulse mode) timing diagram figure 47. parallel i/o data-in/da ta-out timing diagram note: 1. external bus frequency of greater than or equal to 33.34 mhz figure 48. port c interrupt detection timing 25 26 24 23 data out stbo (output) stbi (input) clko data in data out 29 30 31 table 15. port c interrupt timing number characteristic 33.34 mhz unit min max 35 port c interrupt pulse width low (edge-triggered mode) 55 ? ns 36 port c interrupt minimum time between active edges 55 ? ns 35 port c (input) 36
62 TSPC860 [preliminary] 2129b?hirel?12/04 figure 49. idma external requests timing diagram figure 50. sdack timing diagram ? peripheral write, ta sampled low at the falling edge of the clock table 16. idma controller ac elec trical specifications num characteristic all frequencies unit min max 40 dreq setup time to clock high 7 ? ns 41 dreq hold time from clock high 3 ? ns 42 sdack assertion delay from clock high ? 12 ns 43 sdack negation delay from clock low ? 12 ns 44 sdack negation delay from ta low ? 20 ns 45 sdack negation delay from clock high ? 15 ns 46 ta assertion to falling edge of the clock setup time (applies to external ta )7?ns 40 41 clko (output) dreq (input) sdack clko (output) ts (output) rd/wr (output) data ta (output) 42 43 46
63 TSPC860 [preliminary] 2129b?hirel?12/04 figure 51. sdack timing diagram ? peripheral write, ta sampled high at the falling edge of the clock figure 52. sdack timing diagram ? peripheral read 42 44 clko (output) ts (output) rd/wr (output) data ta (output) sdack 42 45 clko (output) ts (output) rd/wr (output) data ta (output) sdack
64 TSPC860 [preliminary] 2129b?hirel?12/04 figure 53. baud rate generator timing diagram figure 54. cpm general-purpose timers timing diagram table 17. baud rate generator ac electrical specifications num characteristic all frequencies unit min max 50 brgo rise and fall time ? 10 ns 51 brgo duty cycle 40 60 % 52 brgo cycle 40 ? ns 51 51 brgox 52 50 50 table 18. timer ac electrical specifications num characteristic all frequencies unit min max 61 tin/tgate rise and fall time 10 ? ns 62 tin/tgate low time 1 ? clk 63 tin/tgate high time 2 ? clk 64 tin/tgate cycle time 3 ? clk 65 clko high to tout valid 3 25 ns clko 60 61 61 65 63 62 64 tin/tgate (input) tout (output)
65 TSPC860 [preliminary] 2129b?hirel?12/04 notes: 1. the ratio syncclk/l1rcl k must be greater than 2.5/1. 2. where p = 1/clkout. thus for a 25 mhz clko1 rate, p = 40 ns. 3. these specs are valid for idl mode only. 4. the strobes and t d on the first bit of the frame becom e valid after l1clk edge or l1sync, whichever comes later. table 19. serial interface ac electrical specifications number characteristic all frequencies unit min max 70 l1rclk, l1tclk frequency (dsc = 0) (1)(3) ? syncclk/2.5 mhz 71 l1rclk, l1tclk width low (dsc = 0) (3) p+10 ns 71a l1rclk, l1tclk width high (dsc = 0) (2) p+10 ? ns 72 l1txd, l1st(1-4), l1rq, l1clko rise/fall time ? 15 ns 73 l1rsync, l1tsync valid to l1clk edge (sync setup time) 20 ? ns 74 l1clk edge to l1rsync, l1tsync invalid (sync hold time) 35 ? ns 75 l1rsync, l1tsync rise/fall time ? 15 ns 76 l1rxd valid to l1clk edge (l1rxd setup time) 17 ? ns 77 l1clk edge to l1rxd invalid (l1rxd hold time) 13 ? ns 78 l1clk edge to l1st(1-4) valid (4) 10 45 ns 78a l1sync valid to l1st(1-4) valid 10 45 ns 79 l1clk edge to l1st(1-4) invalid 10 45 ns 80 l1clk edge to l1txd valid 10 55 ns 80a l1tsync valid to l1txd valid (4) 10 55 ns 81 l1clk edge to l1txd high impedance 0 42 ns 82 l1rclk, l1tclk frequency (dsc = 1) ? 16 or syncclk/2 mhz 83 l1rclk, l1tclk width low (dsc = 1) p+10 ? ns 83a l1rclk, l1tclk width high (dsc = 1) (2) p+10 ? ns 84 l1clk edge to l1clko valid (dsc = 1) ? 30 ns 85 l1rq valid before falling edge of l1tsync (4) 1 ? l1tclk 86 l1gr setup time (3) 42 ? ns 87 l1gr hold time 42 ? ns 88 l1clk edge to l1sync valid (fsd = 00, cnt = 0000, byt = 0, dsc = 0) ?0ns
66 TSPC860 [preliminary] 2129b?hirel?12/04 figure 55. si receive timing diagram with normal clocking (dsc = 0) bit 0 70 75 72 73 74 76 77 71 78 79 rfsd =1 l1rclk (fe = 0, ce = 0) (input) l1st(4-1) (output) 71a l1rclk (fe = 1, ce = 1) (input) l1rsync (input) l1rxd (input)
67 TSPC860 [preliminary] 2129b?hirel?12/04 figure 56. si receive timing with double-speed clocking (dsc = 1) bit 0 rfsd = 1 84 79 78 76 83a 73 75 74 77 72 82 l1rclk (fe = 0, ce = 0) (input) l1st(1-4) (output) l1clko (output) l1rclk (fe = 1, ce = 1) (input) l1rsync (input) l1rxd (input)
68 TSPC860 [preliminary] 2129b?hirel?12/04 figure 57. si transmit timing diagram (dsc = 0) 70 75 72 73 74 71 79 tfsd = 0 80a bit 0 80 78 81 78a l1tclk (fe = 0, ce = 0) (input) l1st(1-4) (output) l1tclk (fe = 1, ce = 1) (input) l1tsync (input) l1txd (output)
69 TSPC860 [preliminary] 2129b?hirel?12/04 figure 58. si transmit timing with double speed clocking (dsc = 1) 72 tfsd=0 75 73 74 78a 80 79 83a 82 84 bit0 78 81 l1rclk (fe = 0, ce = 0) (input) l1st(4-1) (output) l1clko (output) l1rclk (fe = 1, ce = 1) (input) l1rsync (input) l1txd (output)
70 TSPC860 [preliminary] 2129b?hirel?12/04 figure 59. idl timing b17 b16 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m b15 l1rxd (input) l1txd (output) l1st(4-1) (output) l1rq (output) 73 77 123456789 10 11 12 13 14 15 16 17 18 19 20 74 80 b17 b16 b15 b14 b13 b12 b11 b10 d1 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m 71 71 l1gr (input) 78 85 72 76 87 86 l1rsync (input) l1rclk (input) 81
71 TSPC860 [preliminary] 2129b?hirel?12/04 scc in nmsi mode electrical specifications notes: 1. the ratio syncclk/rclk1 and syncclk/ tclk1 must be greater or equal to 2.25/1. 2. also applies to cd and cts hold time when they are used as an external sync signals. notes: 1. the ratios syncclk/rclk1 and synccl k/tclk1 must be greater or equal to 3/1 2. also applies to cd and cts hold time when they are used as an external sync signals. table 20. nmsi external clock timing num characteristic all frequencies unit min max 100 rclk1 and tclk1 width high (1) 1/syncclk ? ns 101 rclk1 and tclk1 width low 1/syncclk + 5 ? ns 102 rclk1 and tclk1 rise/fall time ? 15 ns 103 txd1 active delay (from tclk1 falling edge) 0 50 ns 104 rts1 active/inactive delay (from tclk1 falling edge) 0 50 ns 105 cts1 setup time to tclk1 rising edge 5 ? ns 106 rxd1 setup time to rclk1 rising edge 5 ? ns 107 rxd1 hold time from rclk1 rising edge (2) 5?ns 108 cd1 setup time to rclk1 rising edge 5 ? ns table 21. nmsi internal clock timing num characteristic all frequencies unit min max 100 rclk1 and tclk frequency1 (1) 0 syncclk/3 mhz 102 rclk1 and tclk1 rise/fall time ? ? ns 103 txd1 active delay (from tclk1 falling edge) 0 30 ns 104 rts1 active/inactive delay (from tclk1 falling edge) 0 30 ns 105 cts1 setup time to tclk1 rising edge 40 ? ns 106 rxd1 setup time to rclk1 rising edge 40 ? ns 107 rxd1 hold time from rclk1 rising edge (2) 0?ns 108 cd1 setup time to rclk1 rising edge 40 ? ns
72 TSPC860 [preliminary] 2129b?hirel?12/04 figure 60. scc nmsi receive timing diagram figure 61. scc nmsi transmit timing diagram 101 100 107 108 106 rclk1 rxd1 (input) 107 cd1 (input) cd1 (sync input) 102 102 100 107 105 103 104 104 102 102 101 tclk1 txd1 (output) rts1 (output) cts1 (input) cts1 (sync input)
73 TSPC860 [preliminary] 2129b?hirel?12/04 figure 62. hdlc bus timing diagram notes: 1. the ratio syncclk/rclk1 and syncclk/ tclk1 must be greater or equal to 2/1 2. sdack is asserted whenever the sdma writes the incoming frame da into memory. 100 105 tclk1 txd1 (output) 103 104 104 rts1 (output) 102 102 101 cts1 (echo input) 107 table 22. ethernet electrical specifications number characteristic all frequencies unit min max 120 clsn width high 40 ? ns 121 rclk1 rise/fall time ? 15 ns 122 rclk1 width low 40 ? ns 123 rclk1 clock period (1) 80 120 ns 124 rxd1 setup time 20 ? ns 125 rxd1 hold time 5 ? ns 126 rena active delay (from rclk1 rising edge of the last data bit) 10 ? ns 127 rena width low 100 ? ns 128 tclk1 rise/fall time ? 15 ns 129 tclk1 width low 40 ? ns 130 tclk1 clock period (1) 99 101 ns 131 txd1 active delay (from tclk1 rising edge) 10 50 ns 132 txd1 inactive delay (from tclk1 rising edge) 10 50 ns 133 tena active delay (from tclk1 rising edge) 10 50 ns 134 tena inactive delay (from tclk1 rising edge) 10 50 ns 135 rstrt active delay (from tclk1 falling edge) 10 50 ns 136 rstrt inactive delay (from tclk1 falling edge) 10 50 ns 137 reject width low 1 ? clk 138 clko1 low to sdack asserted (2) ?20ns 139 clko1 low to sdack negated (2) ?20ns
74 TSPC860 [preliminary] 2129b?hirel?12/04 figure 63. ethernet collision timing diagram figure 64. ethernet receive timing diagram figure 65. ethernet transmit timing diagram notes: 1. transmit clock invert (tci) bit in gsmr is set. 2. if rena is deasserted before tena, or rena is not asserted at all during transmit, then the csl bit is set in the buffer descriptor at the end of the frame transmission. 120 clsn (cts1) (input) rclk1 rxd1 (input) rena (cd1) (input) 121 124 125 127 123 126 last bit 121 128 121 132 131 133 134 129 tclk1 txd1 (output) rena (cd1) (input) (note 2) tena (rts1) (input) 128
75 TSPC860 [preliminary] 2129b?hirel?12/04 figure 66. cam interface receive start timing diagram figure 67. cam interface reject timing diagram note: 1. the ratio syncclk/smclk must be greater or equal to 2/1. 0 1 1 bit #1 bit #2 start frame 125 136 rclk1 rxd1 (input) rstrt (output) 137 table 23. smc transparent ac electrical specifications number characteristic all frequencies unit min max 150 smclk clock period (1) 100 ? ns 151 smclk width low 50 ? ns 151a smclk width high 50 ? ns 152 smclk rise/fall time ? 15 ns 153 smtxd active delay (from smclk falling edge) 10 50 ns 154 smrxd/smsync setup time 20 ? ns 155 rxd1/smsync1 hold time 5 ? ns
76 TSPC860 [preliminary] 2129b?hirel?12/04 figure 68. smc transparent timing diagram note: 1. this delay is equal to an integer number of ?character length? clocks. 150 151 151a 152 154 155 155 153 (1) smclk txd1 (output) sync1 rxd1 (input) 152 154 table 24. spi master ac electrical specifications number characteristic all frequencies unit min max 160 master cycle time 4 1024 t cyc 161 master clock (sck) high or low time 2 512 t cyc 162 master data setup time (inputs) 50 ? ns 163 master data hold time (inputs) 0 ? ns 164 master data valid (after sck edge) ? 20 ns 165 master data hold time (outputs) 0 ? ns 166 rise time output ? 15 ns 167 fall time output ? 15 ns
77 TSPC860 [preliminary] 2129b?hirel?12/04 figure 69. spi master (cp = 0) timing diagram figure 70. spi master (cp = 1) timing diagram spiclk ci = 0 output msb data lsb msb 162 167 163 165 164 166 166 167 167 166 161 msb data lsb msb 160 161 spimiso input spimosi output spiclk ci = 1 output 162 167 163 165 164 166 166 167 167 166 161 160 161 msb data lsb msb msb data lsb msb spiclk ci = 0 output spimiso input spimosi output spiclk ci = 1 output
78 TSPC860 [preliminary] 2129b?hirel?12/04 figure 71. spi slave (cp = 0) timing diagram table 25. spi slave ac electrical specifications number characteristic all frequencies unit min max 170 slave cycle time 2 ? tcyc 171 slave enable lead time 15 ? ns 172 slave enable lag time 15 ? ns 173 slave clock (spiclk) high or low time 1 ? tcyc 174 slave sequential transfer delay (does not require deselect) 1?tcyc 175 slave data setup time (inputs) 20 ? ns 176 slave data hold time (inputs) 20 ? ns 177 slave access time ? 50 ns 181 182 181 173 170 173 177 180 181 182 178 179 175 176 182 171 172 174 data data undef lsbin msbin msbout lsbout msbin msbout spiclk ci = 0 input spiclk ci = 1 input spisel input spimiso output spimosi input
79 TSPC860 [preliminary] 2129b?hirel?12/04 figure 72. spi slave (cp = 1) timing diagram notes: 1. scl frequency is given by scl = brgclk _frequency/((brg register + 3 pre_scaler 2) the ratio syncclk/(brgclk/pre_scaler) must be greater or equal to 4/1. spiclk ci = 0 input spiclk ci = 1 input undef 170 174 172 182 181 173 173 171 181 177 179 178 182 180 175 176 181 182 spisel input spimiso output spimosi input data data lsb lsb msb msb msb msb table 26. i 2 c ac electrical specifications ? scl < 100 khz number characteristic all frequencies unit min max 200 scl clock frequency (slave) 0 100 khz 200 scl clock frequency (master) (1) 1.5 100 khz 202 bus free time between transmissions 4.7 ? s 203 low period of scl 4.7 ? s 204 high period of scl 4.0 ? s 205 start condition setup time 4.7 ? s 206 start condition hold time 4.0 ? s 207 data hold time 0 ? s 208 data setup time 250 ? ns 209 sdl/scl rise time ? 1 s 210 sdl/scl fall time ? 300 ns 211 stop condition setup time 4.7 ? s
80 TSPC860 [preliminary] 2129b?hirel?12/04 notes: 1. scl frequency is given by scl = brgclk _frequency/((brg register + 3) pre_scaler the ratio syncclk/(brg_clk/pre_scaler) must be greater or equal to 4/1. figure 73. i 2 c bus timing diagram table 27. i 2 c ac electrical specifications ? scl > 100 khz num characteristic expression min max unit 200 scl clock frequency (slave) fscl 0 brgclk/48 hz 200 scl clock frequency (master) (1) fscl brgclk/16512 brgclk/48 hz 202 bus free time between transmissions 1/(2.2 fscl) ? s 203 low period of scl 1/(2.2 fscl) ? s 204 high period of scl 1/(2.2 fscl) ? s 205 start condition setup time 1/(2.2 fscl) ? s 206 start condition hold time 1/(2.2 fscl) ? s 207 data hold time 0 ? s 208 data setup time 1/(40 fscl) ? s 209 sdl/scl rise time ? 1/(10 fscl) s 210 sdl/scl fall time ? 1/(33 fscl) s 211 stop condition setup time 1/2(2.2 fscl) ? s 202 sda scl 203 204 205 207 208 209 206 210 211
81 TSPC860 [preliminary] 2129b?hirel?12/04 preparation for delivery packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. certificate of compliance atmel offers a certificate of compliances with each shipment of parts, affirming the prod- ucts are in compliance either with mil-std-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. power consideration the average chip-junction temperature, tj, in c can be obtained from the equation: tj = t a + (p d ja ) (1) where t a = ambient temperature, c ja = package thermal resistance, junction to ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o < 0.3 p int and can be neglected. if p i/o is neglected, an approximate relationship between p d and t j is: p d = k (t j + 273 c) (2) solving equations (1) and (2) for k gives: k = p d t (t a + 273 c) + ja p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equa- tion (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . layout practices each v dd pin on the TSPC860 should be provided with a low-impedance path to the board?s supply. each gnd pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v dd power supply should be bypassed to ground using at least four 0.1 f bypass capacitors located as close as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to chip v dd and gnd should be kept to less than half an inch per capacitor lead. a four-layer board, employing two inner layers as v dd and gnd planes is recommended. all output pins on the TSPC860 have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize undershoot and reflec- tions caused by these fast output switching times. this recommendation particularly applies to the address and data busses. maximum pc trace lengths of six inches are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypass- ing becomes especially critical in system s with higher capacitive loads because these loads create higher transient current in the v dd and gnd circuits. pull up all unused inputs or signals that will be inputs during re set. special care should be taken to mini- mize the noise levels on the pll supply pins.
82 TSPC860 [preliminary] 2129b?hirel?12/04 functional units description the TSPC860 powerquicc integrates the embedded powerpc core with high perfor- mance, low power peripherals to extend the freescale data communications family of embedded processors even farther into high end communications and networking prod- ucts. the TSPC860 powerquicc is comprised of three modules which all use the 32-bit internal bus: the embedded powerpc core, the system integration unit (siu), and the communication processor module (cpm). the TSPC860 powerquicc block diagram is shown in figure 1. embedded powerpc core the embedded powerpc core is compliant with the book 1 specification for the pow- erpc architecture. the embedded powerpc core is a fully static design that consists of two functional blocks; the integer block and the load/store block. it executes all integer and load/store operations directly on the hardware. the core supports integer opera- tions on a 32-bit internal data path and 32-bit arithmetic hardware. the core interface to the internal and external buses is 32 bits. the core uses a two instruction load/store queue, a four instruction prefetch queue, and a six instruction history buffer. the core does branch folding and branch prediction with conditional pre-fetch but without condi- tional execution. the embedded powerp c core can operate on 32-bit external operands with one bus cycle. the powerpc integer block supports 32 32-bit fixed point general purpose registers. it can execute one integer instruction each clock cycle. each element in the integer block is clocked only when valid data is present in the data queue ready for operation. this assures that the power consumption of the device is held to the absolute minimum required to perform an operation. the embedded powerpc core is integrated with mmu?s as well as 4 kbyte instruction and data caches. each mmu provides a 32 ent ry, fully associative instruction and data tlb, with multiple page sizes of: 4 kb, 16 kb, 512 kb, 256 kb and 8 mb. it will support 16 virtual address spaces with 8 protection groups. three special registers are available as scratch registers to support software table walk and update.the instruction cache is 4 kilobytes, two-way, set asso ciative with physical addressing. it allows single cycle access on hit with no added latency for miss. it has four words per line, supporting burst line fill using least recently used (lru) replacement. the cache can be locked on a per line basis for application critical routines. the data cache is 4 kilobytes, two-way, set associative with physical addressing. it allows single cycle access on hit with one added clock latency for miss. it has four words per line, supporting burst line fill using lru replacement. the cache can be locked on a per line basis for application critical routines. the data cache can be programmed to support copy-back or write-through via the mmu. the inhibit mode can be programmed per mmu page. the embedded powerpc core with its instruction and data caches delivers approxi- mately 52 mips at 40 mhz, using dhryst one 2.1, based on the assumption that it is issuing one instruction per cycle with a cache hit rate of 94%. the embedded powerpc core contains a much improved debug interface that provides superior debug capabilities without causing any degradation in the speed of operation. this interface supports six watchpoint pins that are used to detect software events. internally it has eight comparators, four of which operate on the effective address on the address bus. the remaining four comparators are split, with two comparators the effec- tive address on the data bus, and two comparators operating on the data on the data bus. the embedded powerpc core can compare using =, , <, > conditions to generate watchpoints. each watchpoint can then generate a breakpoint that can be programmed to trigger in a programmable number of events.
83 TSPC860 [preliminary] 2129b?hirel?12/04 system interface unit (siu) the siu on the TSPC860 powerquicc integr ates general-purpose features useful in almost any 32-bit processor system, enhancing the performance provided by the system integration module (sim) on the ts68en360 quicc device. although the embedded powerpc core is always a 32-bit device internally, it may be configured to operate with an 8-, 16- or 32-bit data bus. regardless of the choice of the system bus size, dynamic bus sizing is supported. bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the 32-bit system bus mode. the siu also provides power management functions, reset control, powerpc decre- menter, powerpc time base and powerpc real time clock. the memory controller will suppo rt up to eight memory ban ks with glueless interfaces to dram, sram, ssram, eprom, flash eprom , srdram, edo and other peripher- als with two-clock access to external sram and bursting support. it provides variable block sizes from 32 kilobytes to 256 megab ytes. the memory cont roller will provide 0 to 15 wait states for each bank of memory and can use address type matching to qualify each memory bank access. it provides f our byte enable signals for varying width devices, one output enable signal and one boot chip select available at reset. the dram interface supports port sizes of 8, 16, and 32 bits. memory banks can be defined in depths of 256k, 512k, 1m, 2m, 4m, 8m, 16m, 32m, or 64m for all port sizes. in addition the memory depth can be defined as 64k and 128k for 8-bit memory or 128m and 256m for 32-bit memory. the dram controller supports page mode access for suc- cessive transfers within bursts. the tspc86 0 will support a glueless interface to one bank of dram while external buffers are required for additional memory banks. the refresh unit provides cas before ras, a programmable refresh timer, refresh active during external reset, disable refresh modes , and stacking up to 7 refresh cycles. the dram interface uses a programmable state machine to support almost any memory interface. pcmcia controller the pcmcia interface is a master (socket) controller and is compliant with release 2.1. the interface will support up to two independe nt pcmcia sockets requiring only exter- nal transceivers/buffers. the interface prov ides 8 memory or i/o windows where each window can be allocated to a particular so cket. if only one pcmcia port is being used, the unused pcmcia port may be used as general-purpose input with interrupt capability. power management the TSPC860 powerquicc supports a wide range of power management features including full on, doze, sleep, deep sleep, and low power stop. in full on mode the TSPC860 processor is fully powered with all internal units operating at the full speed of the processor. a gear mode is provided which is determined by a clock divider, allowing the os to reduce the operational frequency of the processor. doze mode disables core functional units other than the time base decrementer, pll, memory controller, rtc, and then places the cpm in low power standby mode. sleep mode disables everything except the rtc and pit, leaving the pll for lower power but slower wake-up. low power stop disables all logic in the proc essor except the minimum logic required to restart the device, providing the lowest power consumption but requiring the longest wake-up time.
84 TSPC860 [preliminary] 2129b?hirel?12/04 communications processor module (cpm) the TSPC860 powerquicc is the next generation ts68en360 quicc and like its pre- decessor implements a dual processor archit ecture. this dual processor architecture provides both a high performance general purpose processor for application program- ming use as well as a special purpose communication processor (cpm) uniquely designed for communications needs. the cpm contains features that allow t he TSPC860 powerquicc to excel in communi- cations and networking products as did the ts68en360 quicc which preceded it. these features may be divided into three sub-groups: communications processor (cp) sixteen independent dma (sdma) controllers four general-purpose timers the cp provides the communication features of the TSPC860 powerquicc. included are a risc processor, four serial communication controllers (scc) four serial man- agement controllers (smc), one serial peripheral interface (spi), one i 2 interface, 5 kilobytes of dual-port ram, an interrupt cont roller, a time slot assigner, three parallel ports, a parallel interface port, four independent baud rate generators, and sixteen serial dma channels to support the sccs, smcs, spi, and i 2 c. the sdmas provide two chan nels of general-pur pose dma capability for each commu- nications channel. they o ffer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge logic. the four general-purpose timers on the cpm are identical to the timers found on the mc68360 and still support the internal cascading of two ti mers to form a 32-bit timer. the TSPC860 powerquicc maintains the best features of the ts68en360 quicc, while making changes required to provide for the increased flexibility, integration, and performance requested by customers demanding the performance of the powerpc architecture. the addition of a multiply-and -accumulate (mac) function on the cpm fur- ther enhances the TSPC860 powerquicc, enabling various modem and dsp applications. because the cpm architectural approach remains intact between the TSPC860 powerquicc and the ts68en360 quicc, a user of the ts68en360 quicc can easily become familiar with the TSPC860 powerquicc.
85 TSPC860 [preliminary] 2129b?hirel?12/04 software compatibility issues the following list summarizes the major software differences between the ts68en360 quicc and the TSPC860 powerquicc: since the TSPC860 powerquicc uses an embedded powerpc core, code written for the ts68en360 must be recompiled for the powerpc instruction set. code which accesses the ts68en360 peripherals requires only minor modifications for use with the TSPC860. although the functions performed by the powerquicc siu are similar to those performed by the quicc sim, the initialization sequence for the siu is different and therefore code that accesses the siu must be rewritten. many developers of 68k compilers now provide compilers which also support the powerpc architecture. the addition of the mac function to the TSPC860 cpm block to support the needs of higher performance communication software is the only major difference between the cpm on the ts68en360 and that on the TSPC860. therefore the registers used to initialize the quicc cpm are similar to the TSPC860 cpm, but there are some minor changes necessary for supporting the mac function. when porting code from the ts68en360 cpm to the TSPC860 cpm, the software writer will find new options for hardware breakpoint on cpu commands, address, and serial request which are useful for so ftware debugging. support for single step operation with all the registers of the cpm visible makes software development for the cpm on the TSPC860 processor even simpler. TSPC860 powerquicc glueless system design a fundamental design goal of the TSPC860 powerquicc was ease of interface to other system components. figure 72 on page 79 shows a system configuration that offers one eprom, one flash eprom, and supports two dram simms. depending on the capac- itance on the system bus, external buffers may be required. from a logic standpoint, however, a glueless system is maintained. figure 74. TSPC860 system configuration buffer prty[3-0] ras cas[3-0] w (write) data address parity ras ras2 ras1 cas[3-0] powerquicc pc860 cs0 oe data address cs7 we[3-0] ce (enable) oe (output enable) we (write) data address 8-bit boot eprom (flash or regular) e (enable) g (output enable) w (write) data address 16 or 32 bit two dram simms (optional parity) 8, 16 or 32-bit sram
86 TSPC860 [preliminary] 2129b?hirel?12/04 preparation for delivery marking each microcircuit is legible and permanently marked with the following information at minimum: atmel logo manufacturer?s part number class b identification if applicable date-code of inspection lot esd identifier if available country of manufacturing packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. certificate of compliance atmel offers a certificate of compliances with each shipment of parts, affirming the prod- ucts are in compliance either with mil-std-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. handling mos devices must be handled with certain precautions to avoid damage due to accu- mulation of static charge. input protection devices have been designed in the chip to minimize the effect of this static buildup. however, the following handling practices are recommended: a) devices should be handled on benches with conductive and grounded surfaces b) ground test equipment, tools and operator c) do not handle devices by the leads d) store devices in conductive foam or carriers e) avoid use of plastic, ru bber, or silk in mos areas f) maintain relative humidity above 50% if practical package mechanical data package parameters the TSPC860 uses a 25 mm 25 mm, 357 pin plastic ball grid array (pbga) package. the plastic package parameters are as provided in the following list. package outline 25 mm 25 mm interconnects 357 pitch 1.27 mm solder attach 62 sn/36 pb/2 ag solder balls 62 sn/36 pb/2 ag table 28. package description package designator package description zp pbga 357 25*25*0.9p1.27 sq/vr pbga 357 25*25*1.2p1.27
87 TSPC860 [preliminary] 2129b?hirel?12/04 solder balls diameter 0.60 mm ? 0.90 mm maximum module height 2.75 mm co-planarity specification 0.20 mm maximum force 6.0 lbs. total, uniformly distributed over package (5.4 grams/ball) package dimensions figure 75. mechanical dimensions and bottom surface nomenclature of the zp pbga package dim min max millimeters a -- -- -- 2.05 a1 0.50 0.70 a2 0.95 1.35 a3 0.70 0.90 b 0.60 0.90 d 25.00 bsc d1 22.86 bsc d2 22.40 22.60 e 25.00 bsc e1 22.86 bsc e2 e 1.27 bsc d 0.20 a e e1 0.25 c 0.20 c d2 top view e2 a2 a1 bottom view a3 b 18x 4x d1 e b 12345678910111213141516 a b c d e f g h j k l m n p r t 0.03 c a b 0.15 c a 0.35 c c side view 22.40 22.60 19 18 17 u v w m m 357x notes 1. dimensioning and tolerancing per asme y 14.5m, 1994 2. dimensions in millimeters 3. dimension b is the solder ball diameter measured parallel to datum c
88 TSPC860 [preliminary] 2129b?hirel?12/04 figure 76. mechanical dimensions and bottom surface nomenclature of the zq pbga package 25 0.2 b 22.6 22.4 (22.86) bottom view 4x (22.86) 0.9 0.6 12345678910111213141516 a b c d e f g h j k l m n p r t 0.03 a b c 0.15 a 0.35 19 18 17 u v w m m 0.25 a 0.2 a 2.52 2.1 a a 357x a1 index top view 25 c 22.6 22.4 notes: 1. all dimensions in millimeters 2. dimensions and tolerance per asme y14.5m, 1994 3. maximum solder ball diameter measured parallel to datum a side view 1.2 1.1 0.7 0.5 0.62 0.5 357x seating plane + 18x 1.27 3 18x 1.27
89 TSPC860 [preliminary] 2129b?hirel?12/04 ordering information life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can r easonably be expected to result in personal injury. atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indem nify atmel for any damages resulting from such improper use or sale. prototype temperature range: t c m: -55, +125?c v: -40, +110?c pc860 zq u 66 ts (x) md sr version sr prefix for availability of the different versions, contact your sales office type package zp: pbga zq: pbga screening level u: upscreening max internal processor speed 66: 66 mhz revision level d: rev d.4 definitions datasheet status validity objective specification this datasheet contains target and goal specifications for discussion with the customer and application validation before design phase target specification this datasheet contains target or goal specifications for product development valid during the design phase preliminary specification site this datasheet contains preliminary data. additional data may be published at a later date and could include simulation results valid before characterization phase preliminary specification site this datasheet also contains characterization results valid before the industrialization phase product specification this datasheet contains final product specif ications valid for production purpose limiting values limiting values given are in accordance with the absolute maximu m rating system (iec 134). stress above one or more of the limi ting values may cause permanent damage to the device. these are stress ra tings only and operation of the device at these or at any o ther conditions above those given in the characte ristics sections of the specification is not implied. exposure to limiting values f or extended periods may affect device reliability. application information where application information is given, it is advis ory and does not form part of the specification.
90 TSPC860 [preliminary] 2129b?hirel?12/04 document revision history table 29 provides a revision histor y for this hardware specification. table 29. document revision history revision number substantive change(s) b add zq package see ?ordering information? on page 89. a initial revision
i TSPC860 [preliminary] 2129b?hirel?12/04 table of contents features............. ................ .............. ............... .............. .............. .......... 1 description .......... .............. .............. ............... .............. .............. .......... 1 screening/quality ............. .............. ............... .............. .............. .......... 2 general description............. .............. .............. .............. .............. ........ 2 main features ................... .............. ............... .............. .............. ...........3 pin assignment.......... ................. ................ ................. .............. .......... 5 plastic ball grid array........................................................................................... 5 signal description ............... .............. .............. .............. .............. ........ 6 system bus signals .............. ................ ................. ................ ............. 9 active pull-up buffers ......................................................................................... 25 internal pull-up and pull-down resistors............................................................ 26 recommended basic pin connections .............................................................. 26 reset configuration .................................................................................... 26 jtag and debug ports............................................................................... 27 unused inputs............................................................................................. 27 unused outputs .......................................................................................... 27 signal states during hardware reset ................................................................ 27 detailed specifications ....... ................ ................. ................ ............. 28 applicable documents ........ ................ ................. ................ ............. 28 design and construction .................................................................................... 28 terminal connections ................................................................................. 28 lead material and finish.............................................................................. 28 package ...................................................................................................... 29 absolute maximum ratings ................................................................................ 29 absolute maximum rating for the TSPC860 .............................................. 29 electrical characteristics.... ................ ................. ................ ............. 30 general requirements........................................................................................ 30 dc electrical specifications................................................................................ 30 ac electrical specifications control timing........................................................ 32 cpm electrical characteristics ................ ................ .............. ........... 59 pip/pio ac electrical specifications ................. ................ ..............59 scc in nmsi mode electrical specifications ..................................................... 71 preparation for delivery .... ................ ................. ................ ..............81 packaging ........................................................................................................... 81
ii TSPC860 [preliminary] 2129b?hirel?12/04 certificate of compliance .................................................................................... 81 power consideration........... ................ ................. ................ ............. 81 layout practices ................................................................................................. 81 functional units description.. ................. ................ .............. ........... 82 embedded powerpc core .................................................................................. 82 system interface unit (siu) ................................................................................ 83 pcmcia controller ..................................................................................... 83 power management.................................................................................... 83 communications processor module (cpm)................................................ 84 software compatibility issues ............................................................................. 85 TSPC860 powerquicc glueless system design ............................................. 85 preparation for delivery ..... ................ ................. ................ ..............86 marking ............................................................................................................... 86 packaging ........................................................................................................... 86 certificate of compliance..................................................................................... 86 handling .............................................................................................................. 86 package mechanical data .. ................ ................. ................ ..............86 package parameters .......................................................................................... 86 package dimensions .......... ................ ................. ................ ..............87 ordering information ............ ................ ................. ................ ............89 definitions ............. ................ ................ ................. ................ ............89 life support applications .................................................................................... 89 document revision history ................. ................. ................ ............90
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